forked from Minki/linux
Merge branch 'samsung/devel' into next/devel2
This commit is contained in:
Arnd Bergmann
commit
11f0d9311c
@ -716,6 +716,7 @@ config ARCH_S3C64XX
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select CPU_V6
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select ARM_VIC
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select HAVE_CLK
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select HAVE_TCM
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select CLKDEV_LOOKUP
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select NO_IOPORT
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select ARCH_USES_GETTIMEOFFSET
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@ -215,6 +215,7 @@ config MACH_UNIVERSAL_C210
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config MACH_NURI
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bool "Mobile NURI Board"
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select CPU_EXYNOS4210
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select S5P_GPIO_INT
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select S3C_DEV_WDT
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select S3C_DEV_RTC
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select S5P_DEV_FIMD0
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@ -224,15 +225,23 @@ config MACH_NURI
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select S3C_DEV_I2C1
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select S3C_DEV_I2C3
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select S3C_DEV_I2C5
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select S5P_DEV_CSIS0
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select S5P_DEV_FIMC0
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select S5P_DEV_FIMC1
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select S5P_DEV_FIMC2
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select S5P_DEV_FIMC3
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select S5P_DEV_MFC
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select S5P_DEV_USB_EHCI
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select S5P_SETUP_MIPIPHY
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select EXYNOS4_DEV_PD
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select EXYNOS4_SETUP_FIMC
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select EXYNOS4_SETUP_FIMD0
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select EXYNOS4_SETUP_I2C1
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select EXYNOS4_SETUP_I2C3
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select EXYNOS4_SETUP_I2C5
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select EXYNOS4_SETUP_SDHCI
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select EXYNOS4_SETUP_USB_PHY
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select S5P_SETUP_MIPIPHY
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select SAMSUNG_DEV_PWM
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select SAMSUNG_DEV_ADC
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help
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@ -251,11 +260,12 @@ config MACH_ORIGEN
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select S5P_DEV_FIMC3
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select S5P_DEV_FIMD0
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select S5P_DEV_I2C_HDMIPHY
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select S5P_DEV_MFC
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select S5P_DEV_TV
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select S5P_DEV_USB_EHCI
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select EXYNOS4_DEV_PD
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select SAMSUNG_DEV_BACKLIGHT
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select SAMSUNG_DEV_PWM
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select EXYNOS4_DEV_PD
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select EXYNOS4_SETUP_FIMD0
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select EXYNOS4_SETUP_SDHCI
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select EXYNOS4_SETUP_USB_PHY
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@ -27,6 +27,9 @@
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#include <linux/pwm_backlight.h>
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#include <video/platform_lcd.h>
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#include <media/m5mols.h>
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#include <media/s5p_fimc.h>
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#include <media/v4l2-mediabus.h>
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#include <asm/mach/arch.h>
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#include <asm/mach-types.h>
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@ -45,6 +48,9 @@
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#include <plat/iic.h>
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#include <plat/mfc.h>
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#include <plat/pd.h>
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#include <plat/fimc-core.h>
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#include <plat/camport.h>
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#include <plat/mipi_csis.h>
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#include <mach/map.h>
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@ -65,6 +71,8 @@
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enum fixed_regulator_id {
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FIXED_REG_ID_MMC = 0,
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FIXED_REG_ID_MAX8903,
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FIXED_REG_ID_CAM_A28V,
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FIXED_REG_ID_CAM_12V,
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};
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static struct s3c2410_uartcfg nuri_uartcfgs[] __initdata = {
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@ -1066,13 +1074,6 @@ static struct platform_device nuri_max8903_device = {
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},
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};
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static struct device *nuri_cm_devices[] = {
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&s3c_device_i2c5.dev,
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&s3c_device_adc.dev,
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NULL, /* Reserved for UART */
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NULL,
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};
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static void __init nuri_power_init(void)
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{
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int gpio;
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@ -1117,10 +1118,140 @@ static void __init nuri_ehci_init(void)
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s5p_ehci_set_platdata(pdata);
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}
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/* CAMERA */
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static struct regulator_consumer_supply cam_vdda_supply[] = {
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REGULATOR_SUPPLY("a_sensor", "0-001f"),
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};
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static struct regulator_init_data cam_vdda_reg_init_data = {
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.constraints = { .valid_ops_mask = REGULATOR_CHANGE_STATUS },
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.num_consumer_supplies = ARRAY_SIZE(cam_vdda_supply),
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.consumer_supplies = cam_vdda_supply,
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};
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static struct fixed_voltage_config cam_vdda_fixed_voltage_cfg = {
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.supply_name = "CAM_IO_EN",
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.microvolts = 2800000,
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.gpio = EXYNOS4_GPE2(1), /* CAM_IO_EN */
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.enable_high = 1,
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.init_data = &cam_vdda_reg_init_data,
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};
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static struct platform_device cam_vdda_fixed_rdev = {
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.name = "reg-fixed-voltage", .id = FIXED_REG_ID_CAM_A28V,
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.dev = { .platform_data = &cam_vdda_fixed_voltage_cfg },
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};
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static struct regulator_consumer_supply camera_8m_12v_supply =
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REGULATOR_SUPPLY("dig_12", "0-001f");
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static struct regulator_init_data cam_8m_12v_reg_init_data = {
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.num_consumer_supplies = 1,
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.consumer_supplies = &camera_8m_12v_supply,
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.constraints = {
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.valid_ops_mask = REGULATOR_CHANGE_STATUS
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},
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};
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static struct fixed_voltage_config cam_8m_12v_fixed_voltage_cfg = {
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.supply_name = "8M_1.2V",
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.microvolts = 1200000,
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.gpio = EXYNOS4_GPE2(5), /* 8M_1.2V_EN */
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.enable_high = 1,
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.init_data = &cam_8m_12v_reg_init_data,
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};
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static struct platform_device cam_8m_12v_fixed_rdev = {
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.name = "reg-fixed-voltage", .id = FIXED_REG_ID_CAM_12V,
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.dev = { .platform_data = &cam_8m_12v_fixed_voltage_cfg },
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};
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static struct s5p_platform_mipi_csis mipi_csis_platdata = {
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.clk_rate = 166000000UL,
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.lanes = 2,
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.alignment = 32,
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.hs_settle = 12,
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.phy_enable = s5p_csis_phy_enable,
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};
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#define GPIO_CAM_MEGA_RST EXYNOS4_GPY3(7) /* ISP_RESET */
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#define GPIO_CAM_8M_ISP_INT EXYNOS4_GPL2(5)
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static struct m5mols_platform_data m5mols_platdata = {
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.gpio_reset = GPIO_CAM_MEGA_RST,
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};
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static struct i2c_board_info m5mols_board_info = {
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I2C_BOARD_INFO("M5MOLS", 0x1F),
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.platform_data = &m5mols_platdata,
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};
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static struct s5p_fimc_isp_info nuri_camera_sensors[] = {
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{
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.flags = V4L2_MBUS_PCLK_SAMPLE_FALLING |
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V4L2_MBUS_VSYNC_ACTIVE_LOW,
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.bus_type = FIMC_MIPI_CSI2,
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.board_info = &m5mols_board_info,
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.clk_frequency = 24000000UL,
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.csi_data_align = 32,
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},
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};
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static struct s5p_platform_fimc fimc_md_platdata = {
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.isp_info = nuri_camera_sensors,
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.num_clients = ARRAY_SIZE(nuri_camera_sensors),
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};
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static struct gpio nuri_camera_gpios[] = {
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{ GPIO_CAM_8M_ISP_INT, GPIOF_IN, "8M_ISP_INT" },
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{ GPIO_CAM_MEGA_RST, GPIOF_OUT_INIT_LOW, "CAM_8M_NRST" },
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};
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static void nuri_camera_init(void)
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{
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s3c_set_platdata(&mipi_csis_platdata, sizeof(mipi_csis_platdata),
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&s5p_device_mipi_csis0);
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s3c_set_platdata(&fimc_md_platdata, sizeof(fimc_md_platdata),
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&s5p_device_fimc_md);
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if (gpio_request_array(nuri_camera_gpios,
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ARRAY_SIZE(nuri_camera_gpios))) {
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pr_err("%s: GPIO request failed\n", __func__);
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return;
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}
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m5mols_board_info.irq = s5p_register_gpio_interrupt(GPIO_CAM_8M_ISP_INT);
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if (!IS_ERR_VALUE(m5mols_board_info.irq))
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s3c_gpio_cfgpin(GPIO_CAM_8M_ISP_INT, S3C_GPIO_SFN(0xF));
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else
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pr_err("%s: Failed to configure 8M_ISP_INT GPIO\n", __func__);
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/* Free GPIOs controlled directly by the sensor drivers. */
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gpio_free(GPIO_CAM_MEGA_RST);
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if (exynos4_fimc_setup_gpio(S5P_CAMPORT_A)) {
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pr_err("%s: Camera port A setup failed\n", __func__);
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return;
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}
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/* Increase drive strength of the sensor clock output */
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s5p_gpio_set_drvstr(EXYNOS4_GPJ1(3), S5P_GPIO_DRVSTR_LV4);
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}
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static struct s3c2410_platform_i2c nuri_i2c0_platdata __initdata = {
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.frequency = 400000U,
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.sda_delay = 200,
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};
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static struct platform_device *nuri_devices[] __initdata = {
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/* Samsung Platform Devices */
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&s3c_device_i2c5, /* PMIC should initialize first */
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&s3c_device_i2c0,
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&emmc_fixed_voltage,
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&s5p_device_mipi_csis0,
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&s5p_device_fimc0,
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&s5p_device_fimc1,
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&s5p_device_fimc2,
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&s5p_device_fimc3,
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&s5p_device_fimd0,
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&s3c_device_hsmmc0,
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&s3c_device_hsmmc2,
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@ -1137,6 +1268,8 @@ static struct platform_device *nuri_devices[] __initdata = {
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&s5p_device_mfc_r,
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&exynos4_device_pd[PD_MFC],
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&exynos4_device_pd[PD_LCD0],
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&exynos4_device_pd[PD_CAM],
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&s5p_device_fimc_md,
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/* NURI Devices */
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&nuri_gpio_keys,
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@ -1144,6 +1277,8 @@ static struct platform_device *nuri_devices[] __initdata = {
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&nuri_backlight_device,
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&max8903_fixed_reg_dev,
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&nuri_max8903_device,
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&cam_vdda_fixed_rdev,
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&cam_8m_12v_fixed_rdev,
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};
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static void __init nuri_map_io(void)
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@ -1164,6 +1299,7 @@ static void __init nuri_machine_init(void)
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nuri_tsp_init();
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nuri_power_init();
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s3c_i2c0_set_platdata(&nuri_i2c0_platdata);
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i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs));
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s3c_i2c3_set_platdata(&i2c3_data);
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i2c_register_board_info(3, i2c3_devs, ARRAY_SIZE(i2c3_devs));
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@ -1175,6 +1311,8 @@ static void __init nuri_machine_init(void)
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s5p_fimd0_set_platdata(&nuri_fb_pdata);
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nuri_camera_init();
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nuri_ehci_init();
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clk_xusbxti.rate = 24000000;
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@ -1182,6 +1320,12 @@ static void __init nuri_machine_init(void)
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platform_add_devices(nuri_devices, ARRAY_SIZE(nuri_devices));
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s5p_device_mfc.dev.parent = &exynos4_device_pd[PD_MFC].dev;
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s5p_device_fimd0.dev.parent = &exynos4_device_pd[PD_LCD0].dev;
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s5p_device_fimc0.dev.parent = &exynos4_device_pd[PD_CAM].dev;
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s5p_device_fimc1.dev.parent = &exynos4_device_pd[PD_CAM].dev;
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s5p_device_fimc2.dev.parent = &exynos4_device_pd[PD_CAM].dev;
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s5p_device_fimc3.dev.parent = &exynos4_device_pd[PD_CAM].dev;
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s5p_device_mipi_csis0.dev.parent = &exynos4_device_pd[PD_CAM].dev;
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}
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MACHINE_START(NURI, "NURI")
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@ -39,6 +39,7 @@
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#include <plat/backlight.h>
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#include <plat/pd.h>
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#include <plat/fb.h>
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#include <plat/mfc.h>
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#include <mach/map.h>
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@ -89,6 +90,8 @@ static struct s3c2410_uartcfg origen_uartcfgs[] __initdata = {
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static struct regulator_consumer_supply __initdata ldo3_consumer[] = {
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REGULATOR_SUPPLY("vdd11", "s5p-mipi-csis.0"), /* MIPI */
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REGULATOR_SUPPLY("vdd", "exynos4-hdmi"), /* HDMI */
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REGULATOR_SUPPLY("vdd_pll", "exynos4-hdmi"), /* HDMI */
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};
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static struct regulator_consumer_supply __initdata ldo6_consumer[] = {
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REGULATOR_SUPPLY("vdd18", "s5p-mipi-csis.0"), /* MIPI */
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@ -98,6 +101,7 @@ static struct regulator_consumer_supply __initdata ldo7_consumer[] = {
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};
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static struct regulator_consumer_supply __initdata ldo8_consumer[] = {
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REGULATOR_SUPPLY("vdd", "s5p-adc"), /* ADC */
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REGULATOR_SUPPLY("vdd_osc", "exynos4-hdmi"), /* HDMI */
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};
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static struct regulator_consumer_supply __initdata ldo9_consumer[] = {
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REGULATOR_SUPPLY("dvdd", "swb-a31"), /* AR6003 WLAN & CSR 8810 BT */
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@ -598,9 +602,17 @@ static struct platform_device *origen_devices[] __initdata = {
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&s5p_device_fimd0,
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&s5p_device_hdmi,
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&s5p_device_i2c_hdmiphy,
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&s5p_device_mfc,
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&s5p_device_mfc_l,
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&s5p_device_mfc_r,
|
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&s5p_device_mixer,
|
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&exynos4_device_pd[PD_LCD0],
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&exynos4_device_pd[PD_TV],
|
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&exynos4_device_pd[PD_G3D],
|
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&exynos4_device_pd[PD_LCD1],
|
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&exynos4_device_pd[PD_CAM],
|
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&exynos4_device_pd[PD_GPS],
|
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&exynos4_device_pd[PD_MFC],
|
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&origen_device_gpiokeys,
|
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&origen_lcd_hv070wsa,
|
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};
|
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@ -638,6 +650,11 @@ static void __init origen_power_init(void)
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s3c_gpio_setpull(EXYNOS4_GPX0(4), S3C_GPIO_PULL_NONE);
|
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}
|
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|
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static void __init origen_reserve(void)
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{
|
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s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
|
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}
|
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|
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static void __init origen_machine_init(void)
|
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{
|
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origen_power_init();
|
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@ -661,11 +678,14 @@ static void __init origen_machine_init(void)
|
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s5p_fimd0_set_platdata(&origen_lcd_pdata);
|
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|
||||
platform_add_devices(origen_devices, ARRAY_SIZE(origen_devices));
|
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|
||||
s5p_device_fimd0.dev.parent = &exynos4_device_pd[PD_LCD0].dev;
|
||||
|
||||
s5p_device_hdmi.dev.parent = &exynos4_device_pd[PD_TV].dev;
|
||||
s5p_device_mixer.dev.parent = &exynos4_device_pd[PD_TV].dev;
|
||||
|
||||
s5p_device_mfc.dev.parent = &exynos4_device_pd[PD_MFC].dev;
|
||||
|
||||
samsung_bl_set(&origen_bl_gpio_info, &origen_bl_data);
|
||||
}
|
||||
|
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@ -676,4 +696,5 @@ MACHINE_START(ORIGEN, "ORIGEN")
|
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.map_io = origen_map_io,
|
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.init_machine = origen_machine_init,
|
||||
.timer = &exynos4_timer,
|
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.reserve = &origen_reserve,
|
||||
MACHINE_END
|
||||
|
||||
@ -53,7 +53,7 @@
|
||||
#define S3C2410_GPIO_M_NR (32) /* technically 2. */
|
||||
|
||||
#if CONFIG_S3C_GPIO_SPACE != 0
|
||||
#error CONFIG_S3C_GPIO_SPACE cannot be zero at the moment
|
||||
#error CONFIG_S3C_GPIO_SPACE cannot be nonzero at the moment
|
||||
#endif
|
||||
|
||||
#define S3C2410_GPIO_NEXT(__gpio) \
|
||||
|
||||
@ -65,6 +65,7 @@
|
||||
#define S3C2443_CLKDIV0_PREDIV_MASK (3<<4)
|
||||
#define S3C2443_CLKDIV0_PREDIV_SHIFT (4)
|
||||
|
||||
#define S3C2416_CLKDIV0_ARMDIV_MASK (7 << 9)
|
||||
#define S3C2443_CLKDIV0_ARMDIV_MASK (15<<9)
|
||||
#define S3C2443_CLKDIV0_ARMDIV_SHIFT (9)
|
||||
#define S3C2443_CLKDIV0_ARMDIV_1 (0<<9)
|
||||
|
||||
@ -28,6 +28,14 @@
|
||||
#include <mach/regs-clock.h>
|
||||
#include <mach/regs-s3c2443-clock.h>
|
||||
|
||||
/* armdiv
|
||||
*
|
||||
* this clock is sourced from msysclk and can have a number of
|
||||
* divider values applied to it to then be fed into armclk.
|
||||
* The real clock definition is done in s3c2443-clock.c,
|
||||
* only the armdiv divisor table must be defined here.
|
||||
*/
|
||||
|
||||
static unsigned int armdiv[8] = {
|
||||
[0] = 1,
|
||||
[1] = 2,
|
||||
@ -125,16 +133,9 @@ static struct clk hsmmc0_clk = {
|
||||
.ctrlbit = S3C2416_HCLKCON_HSMMC0,
|
||||
};
|
||||
|
||||
static inline unsigned int s3c2416_fclk_div(unsigned long clkcon0)
|
||||
{
|
||||
clkcon0 &= 7 << S3C2443_CLKDIV0_ARMDIV_SHIFT;
|
||||
|
||||
return armdiv[clkcon0 >> S3C2443_CLKDIV0_ARMDIV_SHIFT];
|
||||
}
|
||||
|
||||
void __init_or_cpufreq s3c2416_setup_clocks(void)
|
||||
{
|
||||
s3c2443_common_setup_clocks(s3c2416_get_pll, s3c2416_fclk_div);
|
||||
s3c2443_common_setup_clocks(s3c2416_get_pll);
|
||||
}
|
||||
|
||||
|
||||
@ -158,7 +159,9 @@ void __init s3c2416_init_clocks(int xtal)
|
||||
|
||||
clk_epll.parent = &clk_epllref.clk;
|
||||
|
||||
s3c2443_common_init_clocks(xtal, s3c2416_get_pll, s3c2416_fclk_div);
|
||||
s3c2443_common_init_clocks(xtal, s3c2416_get_pll,
|
||||
armdiv, ARRAY_SIZE(armdiv),
|
||||
S3C2416_CLKDIV0_ARMDIV_MASK);
|
||||
|
||||
for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
|
||||
s3c_register_clksrc(clksrcs[ptr], 1);
|
||||
|
||||
@ -60,6 +60,7 @@
|
||||
#include <plat/iic-core.h>
|
||||
#include <plat/fb-core.h>
|
||||
#include <plat/nand-core.h>
|
||||
#include <plat/adc-core.h>
|
||||
|
||||
static struct map_desc s3c2416_iodesc[] __initdata = {
|
||||
IODESC_ENT(WATCHDOG),
|
||||
@ -97,6 +98,8 @@ int __init s3c2416_init(void)
|
||||
|
||||
s3c_fb_setname("s3c2443-fb");
|
||||
|
||||
s3c_adc_setname("s3c2416-adc");
|
||||
|
||||
register_syscore_ops(&s3c2416_pm_syscore_ops);
|
||||
register_syscore_ops(&s3c24xx_irq_syscore_ops);
|
||||
|
||||
|
||||
@ -61,10 +61,10 @@
|
||||
*
|
||||
* this clock is sourced from msysclk and can have a number of
|
||||
* divider values applied to it to then be fed into armclk.
|
||||
* The real clock definition is done in s3c2443-clock.c,
|
||||
* only the armdiv divisor table must be defined here.
|
||||
*/
|
||||
|
||||
/* armdiv divisor table */
|
||||
|
||||
static unsigned int armdiv[16] = {
|
||||
[S3C2443_CLKDIV0_ARMDIV_1 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 1,
|
||||
[S3C2443_CLKDIV0_ARMDIV_2 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 2,
|
||||
@ -76,92 +76,6 @@ static unsigned int armdiv[16] = {
|
||||
[S3C2443_CLKDIV0_ARMDIV_16 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 16,
|
||||
};
|
||||
|
||||
static inline unsigned int s3c2443_fclk_div(unsigned long clkcon0)
|
||||
{
|
||||
clkcon0 &= S3C2443_CLKDIV0_ARMDIV_MASK;
|
||||
|
||||
return armdiv[clkcon0 >> S3C2443_CLKDIV0_ARMDIV_SHIFT];
|
||||
}
|
||||
|
||||
static unsigned long s3c2443_armclk_roundrate(struct clk *clk,
|
||||
unsigned long rate)
|
||||
{
|
||||
unsigned long parent = clk_get_rate(clk->parent);
|
||||
unsigned long calc;
|
||||
unsigned best = 256; /* bigger than any value */
|
||||
unsigned div;
|
||||
int ptr;
|
||||
|
||||
for (ptr = 0; ptr < ARRAY_SIZE(armdiv); ptr++) {
|
||||
div = armdiv[ptr];
|
||||
calc = parent / div;
|
||||
if (calc <= rate && div < best)
|
||||
best = div;
|
||||
}
|
||||
|
||||
return parent / best;
|
||||
}
|
||||
|
||||
static int s3c2443_armclk_setrate(struct clk *clk, unsigned long rate)
|
||||
{
|
||||
unsigned long parent = clk_get_rate(clk->parent);
|
||||
unsigned long calc;
|
||||
unsigned div;
|
||||
unsigned best = 256; /* bigger than any value */
|
||||
int ptr;
|
||||
int val = -1;
|
||||
|
||||
for (ptr = 0; ptr < ARRAY_SIZE(armdiv); ptr++) {
|
||||
div = armdiv[ptr];
|
||||
calc = parent / div;
|
||||
if (calc <= rate && div < best) {
|
||||
best = div;
|
||||
val = ptr;
|
||||
}
|
||||
}
|
||||
|
||||
if (val >= 0) {
|
||||
unsigned long clkcon0;
|
||||
|
||||
clkcon0 = __raw_readl(S3C2443_CLKDIV0);
|
||||
clkcon0 &= ~S3C2443_CLKDIV0_ARMDIV_MASK;
|
||||
clkcon0 |= val << S3C2443_CLKDIV0_ARMDIV_SHIFT;
|
||||
__raw_writel(clkcon0, S3C2443_CLKDIV0);
|
||||
}
|
||||
|
||||
return (val == -1) ? -EINVAL : 0;
|
||||
}
|
||||
|
||||
static struct clk clk_armdiv = {
|
||||
.name = "armdiv",
|
||||
.parent = &clk_msysclk.clk,
|
||||
.ops = &(struct clk_ops) {
|
||||
.round_rate = s3c2443_armclk_roundrate,
|
||||
.set_rate = s3c2443_armclk_setrate,
|
||||
},
|
||||
};
|
||||
|
||||
/* armclk
|
||||
*
|
||||
* this is the clock fed into the ARM core itself, from armdiv or from hclk.
|
||||
*/
|
||||
|
||||
static struct clk *clk_arm_sources[] = {
|
||||
[0] = &clk_armdiv,
|
||||
[1] = &clk_h,
|
||||
};
|
||||
|
||||
static struct clksrc_clk clk_arm = {
|
||||
.clk = {
|
||||
.name = "armclk",
|
||||
},
|
||||
.sources = &(struct clksrc_sources) {
|
||||
.sources = clk_arm_sources,
|
||||
.nr_sources = ARRAY_SIZE(clk_arm_sources),
|
||||
},
|
||||
.reg_src = { .reg = S3C2443_CLKDIV0, .size = 1, .shift = 13 },
|
||||
};
|
||||
|
||||
/* hsspi
|
||||
*
|
||||
* high-speed spi clock, sourced from esysclk
|
||||
@ -254,25 +168,20 @@ static struct clk init_clocks_off[] = {
|
||||
}
|
||||
};
|
||||
|
||||
static struct clk init_clocks[] = {
|
||||
};
|
||||
|
||||
/* clocks to add straight away */
|
||||
|
||||
static struct clksrc_clk *clksrcs[] __initdata = {
|
||||
&clk_arm,
|
||||
&clk_hsspi,
|
||||
&clk_hsmmc_div,
|
||||
};
|
||||
|
||||
static struct clk *clks[] __initdata = {
|
||||
&clk_hsmmc,
|
||||
&clk_armdiv,
|
||||
};
|
||||
|
||||
void __init_or_cpufreq s3c2443_setup_clocks(void)
|
||||
{
|
||||
s3c2443_common_setup_clocks(s3c2443_get_mpll, s3c2443_fclk_div);
|
||||
s3c2443_common_setup_clocks(s3c2443_get_mpll);
|
||||
}
|
||||
|
||||
void __init s3c2443_init_clocks(int xtal)
|
||||
@ -283,7 +192,9 @@ void __init s3c2443_init_clocks(int xtal)
|
||||
clk_epll.rate = s3c2443_get_epll(epllcon, xtal);
|
||||
clk_epll.parent = &clk_epllref.clk;
|
||||
|
||||
s3c2443_common_init_clocks(xtal, s3c2443_get_mpll, s3c2443_fclk_div);
|
||||
s3c2443_common_init_clocks(xtal, s3c2443_get_mpll,
|
||||
armdiv, ARRAY_SIZE(armdiv),
|
||||
S3C2443_CLKDIV0_ARMDIV_MASK);
|
||||
|
||||
s3c2443_setup_clocks();
|
||||
|
||||
@ -292,10 +203,6 @@ void __init s3c2443_init_clocks(int xtal)
|
||||
for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
|
||||
s3c_register_clksrc(clksrcs[ptr], 1);
|
||||
|
||||
/* register clocks from clock array */
|
||||
|
||||
s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
|
||||
|
||||
/* We must be careful disabling the clocks we are not intending to
|
||||
* be using at boot time, as subsystems such as the LCD which do
|
||||
* their own DMA requests to the bus can cause the system to lockup
|
||||
|
||||
@ -41,6 +41,7 @@
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/fb-core.h>
|
||||
#include <plat/nand-core.h>
|
||||
#include <plat/adc-core.h>
|
||||
|
||||
static struct map_desc s3c2443_iodesc[] __initdata = {
|
||||
IODESC_ENT(WATCHDOG),
|
||||
@ -70,6 +71,8 @@ int __init s3c2443_init(void)
|
||||
s3c_nand_setname("s3c2412-nand");
|
||||
s3c_fb_setname("s3c2443-fb");
|
||||
|
||||
s3c_adc_setname("s3c2443-adc");
|
||||
|
||||
/* change WDT IRQ number */
|
||||
s3c_device_wdt.resource[1].start = IRQ_S3C2443_WDT;
|
||||
s3c_device_wdt.resource[1].end = IRQ_S3C2443_WDT;
|
||||
|
||||
@ -160,6 +160,124 @@ static struct clk clk_prediv = {
|
||||
},
|
||||
};
|
||||
|
||||
/* armdiv
|
||||
*
|
||||
* this clock is sourced from msysclk and can have a number of
|
||||
* divider values applied to it to then be fed into armclk.
|
||||
*/
|
||||
|
||||
static unsigned int *armdiv;
|
||||
static int nr_armdiv;
|
||||
static int armdivmask;
|
||||
|
||||
static unsigned long s3c2443_armclk_roundrate(struct clk *clk,
|
||||
unsigned long rate)
|
||||
{
|
||||
unsigned long parent = clk_get_rate(clk->parent);
|
||||
unsigned long calc;
|
||||
unsigned best = 256; /* bigger than any value */
|
||||
unsigned div;
|
||||
int ptr;
|
||||
|
||||
if (!nr_armdiv)
|
||||
return -EINVAL;
|
||||
|
||||
for (ptr = 0; ptr < nr_armdiv; ptr++) {
|
||||
div = armdiv[ptr];
|
||||
if (div) {
|
||||
/* cpufreq provides 266mhz as 266666000 not 266666666 */
|
||||
calc = (parent / div / 1000) * 1000;
|
||||
if (calc <= rate && div < best)
|
||||
best = div;
|
||||
}
|
||||
}
|
||||
|
||||
return parent / best;
|
||||
}
|
||||
|
||||
static unsigned long s3c2443_armclk_getrate(struct clk *clk)
|
||||
{
|
||||
unsigned long rate = clk_get_rate(clk->parent);
|
||||
unsigned long clkcon0;
|
||||
int val;
|
||||
|
||||
if (!nr_armdiv || !armdivmask)
|
||||
return -EINVAL;
|
||||
|
||||
clkcon0 = __raw_readl(S3C2443_CLKDIV0);
|
||||
clkcon0 &= armdivmask;
|
||||
val = clkcon0 >> S3C2443_CLKDIV0_ARMDIV_SHIFT;
|
||||
|
||||
return rate / armdiv[val];
|
||||
}
|
||||
|
||||
static int s3c2443_armclk_setrate(struct clk *clk, unsigned long rate)
|
||||
{
|
||||
unsigned long parent = clk_get_rate(clk->parent);
|
||||
unsigned long calc;
|
||||
unsigned div;
|
||||
unsigned best = 256; /* bigger than any value */
|
||||
int ptr;
|
||||
int val = -1;
|
||||
|
||||
if (!nr_armdiv || !armdivmask)
|
||||
return -EINVAL;
|
||||
|
||||
for (ptr = 0; ptr < nr_armdiv; ptr++) {
|
||||
div = armdiv[ptr];
|
||||
if (div) {
|
||||
/* cpufreq provides 266mhz as 266666000 not 266666666 */
|
||||
calc = (parent / div / 1000) * 1000;
|
||||
if (calc <= rate && div < best) {
|
||||
best = div;
|
||||
val = ptr;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (val >= 0) {
|
||||
unsigned long clkcon0;
|
||||
|
||||
clkcon0 = __raw_readl(S3C2443_CLKDIV0);
|
||||
clkcon0 &= ~armdivmask;
|
||||
clkcon0 |= val << S3C2443_CLKDIV0_ARMDIV_SHIFT;
|
||||
__raw_writel(clkcon0, S3C2443_CLKDIV0);
|
||||
}
|
||||
|
||||
return (val == -1) ? -EINVAL : 0;
|
||||
}
|
||||
|
||||
static struct clk clk_armdiv = {
|
||||
.name = "armdiv",
|
||||
.parent = &clk_msysclk.clk,
|
||||
.ops = &(struct clk_ops) {
|
||||
.round_rate = s3c2443_armclk_roundrate,
|
||||
.get_rate = s3c2443_armclk_getrate,
|
||||
.set_rate = s3c2443_armclk_setrate,
|
||||
},
|
||||
};
|
||||
|
||||
/* armclk
|
||||
*
|
||||
* this is the clock fed into the ARM core itself, from armdiv or from hclk.
|
||||
*/
|
||||
|
||||
static struct clk *clk_arm_sources[] = {
|
||||
[0] = &clk_armdiv,
|
||||
[1] = &clk_h,
|
||||
};
|
||||
|
||||
static struct clksrc_clk clk_arm = {
|
||||
.clk = {
|
||||
.name = "armclk",
|
||||
},
|
||||
.sources = &(struct clksrc_sources) {
|
||||
.sources = clk_arm_sources,
|
||||
.nr_sources = ARRAY_SIZE(clk_arm_sources),
|
||||
},
|
||||
.reg_src = { .reg = S3C2443_CLKDIV0, .size = 1, .shift = 13 },
|
||||
};
|
||||
|
||||
/* usbhost
|
||||
*
|
||||
* usb host bus-clock, usually 48MHz to provide USB bus clock timing
|
||||
@ -308,6 +426,7 @@ static struct clk init_clocks[] = {
|
||||
.ctrlbit = S3C2443_HCLKCON_DMA5,
|
||||
}, {
|
||||
.name = "hsmmc",
|
||||
.devname = "s3c-sdhci.1",
|
||||
.parent = &clk_h,
|
||||
.enable = s3c2443_clkcon_enable_h,
|
||||
.ctrlbit = S3C2443_HCLKCON_HSMMC,
|
||||
@ -402,8 +521,7 @@ static inline unsigned long s3c2443_get_hdiv(unsigned long clkcon0)
|
||||
|
||||
/* EPLLCON compatible enough to get on/off information */
|
||||
|
||||
void __init_or_cpufreq s3c2443_common_setup_clocks(pll_fn get_mpll,
|
||||
fdiv_fn get_fdiv)
|
||||
void __init_or_cpufreq s3c2443_common_setup_clocks(pll_fn get_mpll)
|
||||
{
|
||||
unsigned long epllcon = __raw_readl(S3C2443_EPLLCON);
|
||||
unsigned long mpllcon = __raw_readl(S3C2443_MPLLCON);
|
||||
@ -423,7 +541,7 @@ void __init_or_cpufreq s3c2443_common_setup_clocks(pll_fn get_mpll,
|
||||
pll = get_mpll(mpllcon, xtal);
|
||||
clk_msysclk.clk.rate = pll;
|
||||
|
||||
fclk = pll / get_fdiv(clkdiv0);
|
||||
fclk = clk_get_rate(&clk_armdiv);
|
||||
hclk = s3c2443_prediv_getrate(&clk_prediv);
|
||||
hclk /= s3c2443_get_hdiv(clkdiv0);
|
||||
pclk = hclk / ((clkdiv0 & S3C2443_CLKDIV0_HALF_PCLK) ? 2 : 1);
|
||||
@ -458,6 +576,7 @@ static struct clk *clks[] __initdata = {
|
||||
&clk_ext,
|
||||
&clk_epll,
|
||||
&clk_usb_bus,
|
||||
&clk_armdiv,
|
||||
};
|
||||
|
||||
static struct clksrc_clk *clksrcs[] __initdata = {
|
||||
@ -467,13 +586,19 @@ static struct clksrc_clk *clksrcs[] __initdata = {
|
||||
&clk_epllref,
|
||||
&clk_esysclk,
|
||||
&clk_msysclk,
|
||||
&clk_arm,
|
||||
};
|
||||
|
||||
void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll,
|
||||
fdiv_fn get_fdiv)
|
||||
unsigned int *divs, int nr_divs,
|
||||
int divmask)
|
||||
{
|
||||
int ptr;
|
||||
|
||||
armdiv = divs;
|
||||
nr_armdiv = nr_divs;
|
||||
armdivmask = divmask;
|
||||
|
||||
/* s3c2443 parents h and p clocks from prediv */
|
||||
clk_h.parent = &clk_prediv;
|
||||
clk_p.parent = &clk_prediv;
|
||||
@ -494,5 +619,5 @@ void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll,
|
||||
s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
|
||||
s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
|
||||
|
||||
s3c2443_common_setup_clocks(get_mpll, get_fdiv);
|
||||
s3c2443_common_setup_clocks(get_mpll);
|
||||
}
|
||||
|
||||
@ -41,6 +41,8 @@
|
||||
|
||||
enum s3c_cpu_type {
|
||||
TYPE_ADCV1, /* S3C24XX */
|
||||
TYPE_ADCV11, /* S3C2443 */
|
||||
TYPE_ADCV12, /* S3C2416, S3C2450 */
|
||||
TYPE_ADCV2, /* S3C64XX, S5P64X0, S5PC100 */
|
||||
TYPE_ADCV3, /* S5PV210, S5PC110, EXYNOS4210 */
|
||||
};
|
||||
@ -98,13 +100,17 @@ static inline void s3c_adc_select(struct adc_device *adc,
|
||||
|
||||
client->select_cb(client, 1);
|
||||
|
||||
con &= ~S3C2410_ADCCON_MUXMASK;
|
||||
if (cpu == TYPE_ADCV1 || cpu == TYPE_ADCV2)
|
||||
con &= ~S3C2410_ADCCON_MUXMASK;
|
||||
con &= ~S3C2410_ADCCON_STDBM;
|
||||
con &= ~S3C2410_ADCCON_STARTMASK;
|
||||
|
||||
if (!client->is_ts) {
|
||||
if (cpu == TYPE_ADCV3)
|
||||
writel(client->channel & 0xf, adc->regs + S5P_ADCMUX);
|
||||
else if (cpu == TYPE_ADCV11 || cpu == TYPE_ADCV12)
|
||||
writel(client->channel & 0xf,
|
||||
adc->regs + S3C2443_ADCMUX);
|
||||
else
|
||||
con |= S3C2410_ADCCON_SELMUX(client->channel);
|
||||
}
|
||||
@ -293,13 +299,13 @@ static irqreturn_t s3c_adc_irq(int irq, void *pw)
|
||||
|
||||
client->nr_samples--;
|
||||
|
||||
if (cpu != TYPE_ADCV1) {
|
||||
/* S3C64XX/S5P ADC resolution is 12-bit */
|
||||
data0 &= 0xfff;
|
||||
data1 &= 0xfff;
|
||||
} else {
|
||||
if (cpu == TYPE_ADCV1 || cpu == TYPE_ADCV11) {
|
||||
data0 &= 0x3ff;
|
||||
data1 &= 0x3ff;
|
||||
} else {
|
||||
/* S3C2416/S3C64XX/S5P ADC resolution is 12-bit */
|
||||
data0 &= 0xfff;
|
||||
data1 &= 0xfff;
|
||||
}
|
||||
|
||||
if (client->convert_cb)
|
||||
@ -320,7 +326,7 @@ static irqreturn_t s3c_adc_irq(int irq, void *pw)
|
||||
}
|
||||
|
||||
exit:
|
||||
if (cpu != TYPE_ADCV1) {
|
||||
if (cpu == TYPE_ADCV2 || cpu == TYPE_ADCV3) {
|
||||
/* Clear ADC interrupt */
|
||||
writel(0, adc->regs + S3C64XX_ADCCLRINT);
|
||||
}
|
||||
@ -332,6 +338,7 @@ static int s3c_adc_probe(struct platform_device *pdev)
|
||||
struct device *dev = &pdev->dev;
|
||||
struct adc_device *adc;
|
||||
struct resource *regs;
|
||||
enum s3c_cpu_type cpu = platform_get_device_id(pdev)->driver_data;
|
||||
int ret;
|
||||
unsigned tmp;
|
||||
|
||||
@ -394,10 +401,13 @@ static int s3c_adc_probe(struct platform_device *pdev)
|
||||
clk_enable(adc->clk);
|
||||
|
||||
tmp = adc->prescale | S3C2410_ADCCON_PRSCEN;
|
||||
if (platform_get_device_id(pdev)->driver_data != TYPE_ADCV1) {
|
||||
/* Enable 12-bit ADC resolution */
|
||||
|
||||
/* Enable 12-bit ADC resolution */
|
||||
if (cpu == TYPE_ADCV12)
|
||||
tmp |= S3C2416_ADCCON_RESSEL;
|
||||
if (cpu == TYPE_ADCV2 || cpu == TYPE_ADCV3)
|
||||
tmp |= S3C64XX_ADCCON_RESSEL;
|
||||
}
|
||||
|
||||
writel(tmp, adc->regs + S3C2410_ADCCON);
|
||||
|
||||
dev_info(dev, "attached adc driver\n");
|
||||
@ -464,6 +474,7 @@ static int s3c_adc_resume(struct device *dev)
|
||||
struct platform_device *pdev = container_of(dev,
|
||||
struct platform_device, dev);
|
||||
struct adc_device *adc = platform_get_drvdata(pdev);
|
||||
enum s3c_cpu_type cpu = platform_get_device_id(pdev)->driver_data;
|
||||
int ret;
|
||||
unsigned long tmp;
|
||||
|
||||
@ -474,9 +485,13 @@ static int s3c_adc_resume(struct device *dev)
|
||||
enable_irq(adc->irq);
|
||||
|
||||
tmp = adc->prescale | S3C2410_ADCCON_PRSCEN;
|
||||
|
||||
/* Enable 12-bit ADC resolution */
|
||||
if (platform_get_device_id(pdev)->driver_data != TYPE_ADCV1)
|
||||
if (cpu == TYPE_ADCV12)
|
||||
tmp |= S3C2416_ADCCON_RESSEL;
|
||||
if (cpu == TYPE_ADCV2 || cpu == TYPE_ADCV3)
|
||||
tmp |= S3C64XX_ADCCON_RESSEL;
|
||||
|
||||
writel(tmp, adc->regs + S3C2410_ADCCON);
|
||||
|
||||
return 0;
|
||||
@ -491,6 +506,12 @@ static struct platform_device_id s3c_adc_driver_ids[] = {
|
||||
{
|
||||
.name = "s3c24xx-adc",
|
||||
.driver_data = TYPE_ADCV1,
|
||||
}, {
|
||||
.name = "s3c2443-adc",
|
||||
.driver_data = TYPE_ADCV11,
|
||||
}, {
|
||||
.name = "s3c2416-adc",
|
||||
.driver_data = TYPE_ADCV12,
|
||||
}, {
|
||||
.name = "s3c64xx-adc",
|
||||
.driver_data = TYPE_ADCV2,
|
||||
|
||||
@ -20,7 +20,7 @@
|
||||
/* re-define device name depending on support. */
|
||||
static inline void s3c_adc_setname(char *name)
|
||||
{
|
||||
#ifdef CONFIG_SAMSUNG_DEV_ADC
|
||||
#if defined(CONFIG_SAMSUNG_DEV_ADC) || defined(CONFIG_PLAT_S3C24XX)
|
||||
s3c_device_adc.name = name;
|
||||
#endif
|
||||
}
|
||||
|
||||
@ -25,7 +25,6 @@ extern unsigned long samsung_cpu_id;
|
||||
|
||||
#define S3C6400_CPU_ID 0x36400000
|
||||
#define S3C6410_CPU_ID 0x36410000
|
||||
#define S3C64XX_CPU_ID (S3C6400_CPU_ID & S3C6410_CPU_ID)
|
||||
#define S3C64XX_CPU_MASK 0xFFFFF000
|
||||
|
||||
#define S5P6440_CPU_ID 0x56440000
|
||||
@ -50,7 +49,8 @@ static inline int is_samsung_##name(void) \
|
||||
}
|
||||
|
||||
IS_SAMSUNG_CPU(s3c24xx, S3C24XX_CPU_ID, S3C24XX_CPU_MASK)
|
||||
IS_SAMSUNG_CPU(s3c64xx, S3C64XX_CPU_ID, S3C64XX_CPU_MASK)
|
||||
IS_SAMSUNG_CPU(s3c6400, S3C6400_CPU_ID, S3C64XX_CPU_MASK)
|
||||
IS_SAMSUNG_CPU(s3c6410, S3C6410_CPU_ID, S3C64XX_CPU_MASK)
|
||||
IS_SAMSUNG_CPU(s5p6440, S5P6440_CPU_ID, S5P64XX_CPU_MASK)
|
||||
IS_SAMSUNG_CPU(s5p6450, S5P6450_CPU_ID, S5P64XX_CPU_MASK)
|
||||
IS_SAMSUNG_CPU(s5pc100, S5PC100_CPU_ID, S5PC100_CPU_MASK)
|
||||
@ -69,7 +69,7 @@ IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
|
||||
# define soc_is_s3c64xx() is_samsung_s3c64xx()
|
||||
# define soc_is_s3c64xx() (is_samsung_s3c6400() || is_samsung_s3c6410())
|
||||
#else
|
||||
# define soc_is_s3c64xx() 0
|
||||
#endif
|
||||
|
||||
@ -20,6 +20,7 @@
|
||||
#define S3C2410_ADCDAT0 S3C2410_ADCREG(0x0C)
|
||||
#define S3C2410_ADCDAT1 S3C2410_ADCREG(0x10)
|
||||
#define S3C64XX_ADCUPDN S3C2410_ADCREG(0x14)
|
||||
#define S3C2443_ADCMUX S3C2410_ADCREG(0x18)
|
||||
#define S3C64XX_ADCCLRINT S3C2410_ADCREG(0x18)
|
||||
#define S5P_ADCMUX S3C2410_ADCREG(0x1C)
|
||||
#define S3C64XX_ADCCLRINTPNDNUP S3C2410_ADCREG(0x20)
|
||||
@ -33,6 +34,7 @@
|
||||
#define S3C2410_ADCCON_PRSCVLMASK (0xFF<<6)
|
||||
#define S3C2410_ADCCON_SELMUX(x) (((x)&0x7)<<3)
|
||||
#define S3C2410_ADCCON_MUXMASK (0x7<<3)
|
||||
#define S3C2416_ADCCON_RESSEL (1 << 3)
|
||||
#define S3C2410_ADCCON_STDBM (1<<2)
|
||||
#define S3C2410_ADCCON_READ_START (1<<1)
|
||||
#define S3C2410_ADCCON_ENABLE_START (1<<0)
|
||||
@ -40,6 +42,7 @@
|
||||
|
||||
|
||||
/* ADCTSC Register Bits */
|
||||
#define S3C2443_ADCTSC_UD_SEN (1 << 8)
|
||||
#define S3C2410_ADCTSC_YM_SEN (1<<7)
|
||||
#define S3C2410_ADCTSC_YP_SEN (1<<6)
|
||||
#define S3C2410_ADCTSC_XM_SEN (1<<5)
|
||||
|
||||
@ -37,10 +37,11 @@ extern int s3c2443_baseclk_add(void);
|
||||
struct clk; /* some files don't need clk.h otherwise */
|
||||
|
||||
typedef unsigned int (*pll_fn)(unsigned int reg, unsigned int base);
|
||||
typedef unsigned int (*fdiv_fn)(unsigned long clkcon0);
|
||||
|
||||
extern void s3c2443_common_setup_clocks(pll_fn get_mpll, fdiv_fn fdiv);
|
||||
extern void s3c2443_common_init_clocks(int xtal, pll_fn get_mpll, fdiv_fn fdiv);
|
||||
extern void s3c2443_common_setup_clocks(pll_fn get_mpll);
|
||||
extern void s3c2443_common_init_clocks(int xtal, pll_fn get_mpll,
|
||||
unsigned int *divs, int nr_divs,
|
||||
int divmask);
|
||||
|
||||
extern int s3c2443_clkcon_enable_h(struct clk *clk, int enable);
|
||||
extern int s3c2443_clkcon_enable_p(struct clk *clk, int enable);
|
||||
|
||||
@ -318,6 +318,7 @@ static unsigned samsung_gpio_getcfg_4bit(struct samsung_gpio_chip *chip,
|
||||
return S3C_GPIO_SPECIAL(con);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PLAT_S3C24XX
|
||||
/*
|
||||
* s3c24xx_gpio_setcfg_abank - S3C24XX style GPIO configuration (Bank A)
|
||||
* @chip: The gpio chip that is being configured.
|
||||
@ -379,7 +380,9 @@ static unsigned s3c24xx_gpio_getcfg_abank(struct samsung_gpio_chip *chip,
|
||||
|
||||
return S3C_GPIO_SFN(con);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_CPU_S5P6440) || defined(CONFIG_CPU_S5P6450)
|
||||
static int s5p64x0_gpio_setcfg_rbank(struct samsung_gpio_chip *chip,
|
||||
unsigned int off, unsigned int cfg)
|
||||
{
|
||||
@ -417,6 +420,7 @@ static int s5p64x0_gpio_setcfg_rbank(struct samsung_gpio_chip *chip,
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
static void __init samsung_gpiolib_set_cfg(struct samsung_gpio_cfg *chipcfg,
|
||||
int nr_chips)
|
||||
@ -438,10 +442,12 @@ struct samsung_gpio_cfg s3c24xx_gpiocfg_default = {
|
||||
.get_config = samsung_gpio_getcfg_2bit,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_PLAT_S3C24XX
|
||||
static struct samsung_gpio_cfg s3c24xx_gpiocfg_banka = {
|
||||
.set_config = s3c24xx_gpio_setcfg_abank,
|
||||
.get_config = s3c24xx_gpio_getcfg_abank,
|
||||
};
|
||||
#endif
|
||||
|
||||
static struct samsung_gpio_cfg exynos4_gpio_cfg = {
|
||||
.set_pull = exynos4_gpio_setpull,
|
||||
@ -450,6 +456,7 @@ static struct samsung_gpio_cfg exynos4_gpio_cfg = {
|
||||
.get_config = samsung_gpio_getcfg_4bit,
|
||||
};
|
||||
|
||||
#if defined(CONFIG_CPU_S5P6440) || defined(CONFIG_CPU_S5P6450)
|
||||
static struct samsung_gpio_cfg s5p64x0_gpio_cfg_rbank = {
|
||||
.cfg_eint = 0x3,
|
||||
.set_config = s5p64x0_gpio_setcfg_rbank,
|
||||
@ -457,6 +464,7 @@ static struct samsung_gpio_cfg s5p64x0_gpio_cfg_rbank = {
|
||||
.set_pull = samsung_gpio_setpull_updown,
|
||||
.get_pull = samsung_gpio_getpull_updown,
|
||||
};
|
||||
#endif
|
||||
|
||||
static struct samsung_gpio_cfg samsung_gpio_cfgs[] = {
|
||||
{
|
||||
@ -482,7 +490,14 @@ static struct samsung_gpio_cfg samsung_gpio_cfgs[] = {
|
||||
}, {
|
||||
.set_config = samsung_gpio_setcfg_2bit,
|
||||
.get_config = samsung_gpio_getcfg_2bit,
|
||||
},
|
||||
}, {
|
||||
.set_pull = exynos4_gpio_setpull,
|
||||
.get_pull = exynos4_gpio_getpull,
|
||||
}, {
|
||||
.cfg_eint = 0x3,
|
||||
.set_pull = exynos4_gpio_setpull,
|
||||
.get_pull = exynos4_gpio_getpull,
|
||||
}
|
||||
};
|
||||
|
||||
/*
|
||||
@ -682,6 +697,7 @@ static int samsung_gpiolib_4bit2_output(struct gpio_chip *chip,
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PLAT_S3C24XX
|
||||
/* The next set of routines are for the case of s3c24xx bank a */
|
||||
|
||||
static int s3c24xx_gpiolib_banka_input(struct gpio_chip *chip, unsigned offset)
|
||||
@ -717,6 +733,7 @@ static int s3c24xx_gpiolib_banka_output(struct gpio_chip *chip,
|
||||
local_irq_restore(flags);
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* The next set of routines are for the case of s5p64x0 bank r */
|
||||
|
||||
@ -914,6 +931,10 @@ static void __init s3c24xx_gpiolib_add_chips(struct samsung_gpio_chip *chip,
|
||||
struct gpio_chip *gc = &chip->chip;
|
||||
|
||||
for (i = 0 ; i < nr_chips; i++, chip++) {
|
||||
/* skip banks not present on SoC */
|
||||
if (chip->chip.base >= S3C_GPIO_END)
|
||||
continue;
|
||||
|
||||
if (!chip->config)
|
||||
chip->config = &s3c24xx_gpiocfg_default;
|
||||
if (!chip->pm)
|
||||
@ -2249,49 +2270,49 @@ static struct samsung_gpio_chip exynos4_gpios_2[] = {
|
||||
.label = "GPL2",
|
||||
},
|
||||
}, {
|
||||
.config = &samsung_gpio_cfgs[0],
|
||||
.config = &samsung_gpio_cfgs[8],
|
||||
.chip = {
|
||||
.base = EXYNOS4_GPY0(0),
|
||||
.ngpio = EXYNOS4_GPIO_Y0_NR,
|
||||
.label = "GPY0",
|
||||
},
|
||||
}, {
|
||||
.config = &samsung_gpio_cfgs[0],
|
||||
.config = &samsung_gpio_cfgs[8],
|
||||
.chip = {
|
||||
.base = EXYNOS4_GPY1(0),
|
||||
.ngpio = EXYNOS4_GPIO_Y1_NR,
|
||||
.label = "GPY1",
|
||||
},
|
||||
}, {
|
||||
.config = &samsung_gpio_cfgs[0],
|
||||
.config = &samsung_gpio_cfgs[8],
|
||||
.chip = {
|
||||
.base = EXYNOS4_GPY2(0),
|
||||
.ngpio = EXYNOS4_GPIO_Y2_NR,
|
||||
.label = "GPY2",
|
||||
},
|
||||
}, {
|
||||
.config = &samsung_gpio_cfgs[0],
|
||||
.config = &samsung_gpio_cfgs[8],
|
||||
.chip = {
|
||||
.base = EXYNOS4_GPY3(0),
|
||||
.ngpio = EXYNOS4_GPIO_Y3_NR,
|
||||
.label = "GPY3",
|
||||
},
|
||||
}, {
|
||||
.config = &samsung_gpio_cfgs[0],
|
||||
.config = &samsung_gpio_cfgs[8],
|
||||
.chip = {
|
||||
.base = EXYNOS4_GPY4(0),
|
||||
.ngpio = EXYNOS4_GPIO_Y4_NR,
|
||||
.label = "GPY4",
|
||||
},
|
||||
}, {
|
||||
.config = &samsung_gpio_cfgs[0],
|
||||
.config = &samsung_gpio_cfgs[8],
|
||||
.chip = {
|
||||
.base = EXYNOS4_GPY5(0),
|
||||
.ngpio = EXYNOS4_GPIO_Y5_NR,
|
||||
.label = "GPY5",
|
||||
},
|
||||
}, {
|
||||
.config = &samsung_gpio_cfgs[0],
|
||||
.config = &samsung_gpio_cfgs[8],
|
||||
.chip = {
|
||||
.base = EXYNOS4_GPY6(0),
|
||||
.ngpio = EXYNOS4_GPIO_Y6_NR,
|
||||
@ -2299,7 +2320,7 @@ static struct samsung_gpio_chip exynos4_gpios_2[] = {
|
||||
},
|
||||
}, {
|
||||
.base = (S5P_VA_GPIO2 + 0xC00),
|
||||
.config = &samsung_gpio_cfgs[3],
|
||||
.config = &samsung_gpio_cfgs[9],
|
||||
.irq_base = IRQ_EINT(0),
|
||||
.chip = {
|
||||
.base = EXYNOS4_GPX0(0),
|
||||
@ -2309,7 +2330,7 @@ static struct samsung_gpio_chip exynos4_gpios_2[] = {
|
||||
},
|
||||
}, {
|
||||
.base = (S5P_VA_GPIO2 + 0xC20),
|
||||
.config = &samsung_gpio_cfgs[3],
|
||||
.config = &samsung_gpio_cfgs[9],
|
||||
.irq_base = IRQ_EINT(8),
|
||||
.chip = {
|
||||
.base = EXYNOS4_GPX1(0),
|
||||
@ -2319,7 +2340,7 @@ static struct samsung_gpio_chip exynos4_gpios_2[] = {
|
||||
},
|
||||
}, {
|
||||
.base = (S5P_VA_GPIO2 + 0xC40),
|
||||
.config = &samsung_gpio_cfgs[3],
|
||||
.config = &samsung_gpio_cfgs[9],
|
||||
.irq_base = IRQ_EINT(16),
|
||||
.chip = {
|
||||
.base = EXYNOS4_GPX2(0),
|
||||
@ -2329,7 +2350,7 @@ static struct samsung_gpio_chip exynos4_gpios_2[] = {
|
||||
},
|
||||
}, {
|
||||
.base = (S5P_VA_GPIO2 + 0xC60),
|
||||
.config = &samsung_gpio_cfgs[3],
|
||||
.config = &samsung_gpio_cfgs[9],
|
||||
.irq_base = IRQ_EINT(24),
|
||||
.chip = {
|
||||
.base = EXYNOS4_GPX3(0),
|
||||
@ -2465,6 +2486,9 @@ static __init int samsung_gpiolib_init(void)
|
||||
s5p_register_gpioint_bank(IRQ_GPIO_XA, 0, IRQ_GPIO1_NR_GROUPS);
|
||||
s5p_register_gpioint_bank(IRQ_GPIO_XB, IRQ_GPIO1_NR_GROUPS, IRQ_GPIO2_NR_GROUPS);
|
||||
#endif
|
||||
} else {
|
||||
WARN(1, "Unknown SoC in gpio-samsung, no GPIOs added\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user