forked from Minki/linux
PCI hotplug: shpchp: use generic pci_configure_slot()
Use the generic pci_configure_slot() rather than the SHPC-specific program_fw_provided_values(). Unlike the previous SHPC-specific code, pci_configure_slot() programs PCIe settings when an _HPX method provides them, so if it's possible to have an SHPC-managed PCIe device, it can now be configured. Signed-off-by: Bjorn Helgaas <bjorn.helgaas@hp.com> Reviewed-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Acked-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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@ -188,19 +188,12 @@ static inline const char *slot_name(struct slot *slot)
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#ifdef CONFIG_ACPI
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#include <linux/pci-acpi.h>
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static inline int get_hp_params_from_firmware(struct pci_dev *dev,
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struct hotplug_params *hpp)
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{
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return acpi_get_hp_params_from_firmware(dev, hpp);
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}
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static inline int get_hp_hw_control_from_firmware(struct pci_dev *dev)
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{
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u32 flags = OSC_SHPC_NATIVE_HP_CONTROL;
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return acpi_get_hp_hw_control_from_firmware(dev, flags);
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}
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#else
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#define get_hp_params_from_firmware(dev, hpp) (-ENODEV)
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#define get_hp_hw_control_from_firmware(dev) (0)
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#endif
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@ -34,66 +34,6 @@
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#include "../pci.h"
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#include "shpchp.h"
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static void program_fw_provided_values(struct pci_dev *dev)
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{
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u16 pci_cmd, pci_bctl;
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struct pci_dev *cdev;
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struct hotplug_params hpp;
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/* Program hpp values for this device */
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if (!(dev->hdr_type == PCI_HEADER_TYPE_NORMAL ||
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(dev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
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(dev->class >> 8) == PCI_CLASS_BRIDGE_PCI)))
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return;
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/* use default values if we can't get them from firmware */
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if (get_hp_params_from_firmware(dev, &hpp) ||
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!hpp.t0 || (hpp.t0->revision > 1)) {
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warn("Could not get hotplug parameters. Use defaults\n");
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hpp.t0 = &hpp.type0_data;
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hpp.t0->revision = 0;
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hpp.t0->cache_line_size = 8;
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hpp.t0->latency_timer = 0x40;
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hpp.t0->enable_serr = 0;
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hpp.t0->enable_perr = 0;
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}
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pci_write_config_byte(dev,
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PCI_CACHE_LINE_SIZE, hpp.t0->cache_line_size);
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pci_write_config_byte(dev, PCI_LATENCY_TIMER, hpp.t0->latency_timer);
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pci_read_config_word(dev, PCI_COMMAND, &pci_cmd);
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if (hpp.t0->enable_serr)
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pci_cmd |= PCI_COMMAND_SERR;
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else
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pci_cmd &= ~PCI_COMMAND_SERR;
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if (hpp.t0->enable_perr)
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pci_cmd |= PCI_COMMAND_PARITY;
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else
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pci_cmd &= ~PCI_COMMAND_PARITY;
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pci_write_config_word(dev, PCI_COMMAND, pci_cmd);
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/* Program bridge control value and child devices */
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if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
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pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER,
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hpp.t0->latency_timer);
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pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &pci_bctl);
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if (hpp.t0->enable_serr)
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pci_bctl |= PCI_BRIDGE_CTL_SERR;
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else
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pci_bctl &= ~PCI_BRIDGE_CTL_SERR;
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if (hpp.t0->enable_perr)
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pci_bctl |= PCI_BRIDGE_CTL_PARITY;
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else
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pci_bctl &= ~PCI_BRIDGE_CTL_PARITY;
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pci_write_config_word(dev, PCI_BRIDGE_CONTROL, pci_bctl);
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if (dev->subordinate) {
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list_for_each_entry(cdev, &dev->subordinate->devices,
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bus_list)
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program_fw_provided_values(cdev);
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}
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}
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}
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int __ref shpchp_configure_device(struct slot *p_slot)
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{
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struct pci_dev *dev;
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@ -153,7 +93,7 @@ int __ref shpchp_configure_device(struct slot *p_slot)
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child->subordinate = pci_do_scan_bus(child);
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pci_bus_size_bridges(child);
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}
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program_fw_provided_values(dev);
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pci_configure_slot(dev);
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pci_dev_put(dev);
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}
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