forked from Minki/linux
x86: complete move ACPI from mpparse.c
Signed-off-by: Alexey Starikovskiy <astarikovskiy@suse.de> Signed-off-by: Ingo Molnar <mingo@elte.hu>
This commit is contained in:
Alexey Starikovskiy
Thomas Gleixner
parent
32c5061265
commit
11113f84c7
@ -846,6 +846,310 @@ static int __init acpi_parse_madt_lapic_entries(void)
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#endif /* CONFIG_X86_LOCAL_APIC */
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#ifdef CONFIG_X86_IO_APIC
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#define MP_ISA_BUS 0
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#if defined(CONFIG_X86_ES7000) || defined(CONFIG_X86_GENERICARCH)
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extern int es7000_plat;
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#endif
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static struct mp_ioapic_routing mp_ioapic_routing[MAX_IO_APICS];
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static int mp_find_ioapic(int gsi)
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{
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int i = 0;
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/* Find the IOAPIC that manages this GSI. */
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for (i = 0; i < nr_ioapics; i++) {
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if ((gsi >= mp_ioapic_routing[i].gsi_base)
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&& (gsi <= mp_ioapic_routing[i].gsi_end))
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return i;
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}
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printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
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return -1;
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}
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static u8 __init uniq_ioapic_id(u8 id)
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{
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#ifdef CONFIG_X86_32
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if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
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!APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
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return io_apic_get_unique_id(nr_ioapics, id);
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else
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return id;
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#else
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int i;
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DECLARE_BITMAP(used, 256);
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bitmap_zero(used, 256);
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for (i = 0; i < nr_ioapics; i++) {
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struct mpc_config_ioapic *ia = &mp_ioapics[i];
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__set_bit(ia->mpc_apicid, used);
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}
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if (!test_bit(id, used))
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return id;
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return find_first_zero_bit(used, 256);
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#endif
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}
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static int bad_ioapic(unsigned long address)
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{
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if (nr_ioapics >= MAX_IO_APICS) {
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printk(KERN_ERR "ERROR: Max # of I/O APICs (%d) exceeded "
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"(found %d)\n", MAX_IO_APICS, nr_ioapics);
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panic("Recompile kernel with bigger MAX_IO_APICS!\n");
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}
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if (!address) {
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printk(KERN_ERR "WARNING: Bogus (zero) I/O APIC address"
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" found in table, skipping!\n");
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return 1;
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}
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return 0;
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}
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void __init mp_register_ioapic(int id, u32 address, u32 gsi_base)
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{
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int idx = 0;
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if (bad_ioapic(address))
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return;
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idx = nr_ioapics;
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mp_ioapics[idx].mpc_type = MP_IOAPIC;
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mp_ioapics[idx].mpc_flags = MPC_APIC_USABLE;
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mp_ioapics[idx].mpc_apicaddr = address;
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set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
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mp_ioapics[idx].mpc_apicid = uniq_ioapic_id(id);
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#ifdef CONFIG_X86_32
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mp_ioapics[idx].mpc_apicver = io_apic_get_version(idx);
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#else
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mp_ioapics[idx].mpc_apicver = 0;
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#endif
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/*
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* Build basic GSI lookup table to facilitate gsi->io_apic lookups
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* and to prevent reprogramming of IOAPIC pins (PCI GSIs).
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*/
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mp_ioapic_routing[idx].apic_id = mp_ioapics[idx].mpc_apicid;
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mp_ioapic_routing[idx].gsi_base = gsi_base;
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mp_ioapic_routing[idx].gsi_end = gsi_base +
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io_apic_get_redir_entries(idx);
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printk(KERN_INFO "IOAPIC[%d]: apic_id %d, version %d, address 0x%x, "
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"GSI %d-%d\n", idx, mp_ioapics[idx].mpc_apicid,
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mp_ioapics[idx].mpc_apicver, mp_ioapics[idx].mpc_apicaddr,
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mp_ioapic_routing[idx].gsi_base, mp_ioapic_routing[idx].gsi_end);
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nr_ioapics++;
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}
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void __init mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger, u32 gsi)
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{
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int ioapic = -1;
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int pin = -1;
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/*
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* Convert 'gsi' to 'ioapic.pin'.
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*/
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ioapic = mp_find_ioapic(gsi);
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if (ioapic < 0)
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return;
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pin = gsi - mp_ioapic_routing[ioapic].gsi_base;
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/*
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* TBD: This check is for faulty timer entries, where the override
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* erroneously sets the trigger to level, resulting in a HUGE
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* increase of timer interrupts!
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*/
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if ((bus_irq == 0) && (trigger == 3))
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trigger = 1;
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mp_irqs[mp_irq_entries].mpc_type = MP_INTSRC;
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mp_irqs[mp_irq_entries].mpc_irqtype = mp_INT;
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mp_irqs[mp_irq_entries].mpc_irqflag = (trigger << 2) | polarity;
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mp_irqs[mp_irq_entries].mpc_srcbus = MP_ISA_BUS;
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mp_irqs[mp_irq_entries].mpc_srcbusirq = bus_irq; /* IRQ */
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mp_irqs[mp_irq_entries].mpc_dstapic =
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mp_ioapics[ioapic].mpc_apicid; /* APIC ID */
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mp_irqs[mp_irq_entries].mpc_dstirq = pin; /* INTIN# */
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if (++mp_irq_entries == MAX_IRQ_SOURCES)
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panic("Max # of irq sources exceeded!!\n");
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}
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void __init mp_config_acpi_legacy_irqs(void)
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{
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int i = 0;
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int ioapic = -1;
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#if defined (CONFIG_MCA) || defined (CONFIG_EISA)
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/*
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* Fabricate the legacy ISA bus (bus #31).
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*/
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mp_bus_id_to_type[MP_ISA_BUS] = MP_BUS_ISA;
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#endif
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set_bit(MP_ISA_BUS, mp_bus_not_pci);
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Dprintk("Bus #%d is ISA\n", MP_ISA_BUS);
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#if defined(CONFIG_X86_ES7000) || defined(CONFIG_X86_GENERICARCH)
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/*
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* Older generations of ES7000 have no legacy identity mappings
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*/
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if (es7000_plat == 1)
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return;
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#endif
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/*
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* Locate the IOAPIC that manages the ISA IRQs (0-15).
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*/
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ioapic = mp_find_ioapic(0);
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if (ioapic < 0)
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return;
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mp_irqs[mp_irq_entries].mpc_type = MP_INTSRC;
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mp_irqs[mp_irq_entries].mpc_irqflag = 0; /* Conforming */
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mp_irqs[mp_irq_entries].mpc_srcbus = MP_ISA_BUS;
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#ifdef CONFIG_X86_IO_APIC
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mp_irqs[mp_irq_entries].mpc_dstapic = mp_ioapics[ioapic].mpc_apicid;
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#endif
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/*
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* Use the default configuration for the IRQs 0-15. Unless
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* overridden by (MADT) interrupt source override entries.
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*/
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for (i = 0; i < 16; i++) {
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int idx;
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for (idx = 0; idx < mp_irq_entries; idx++) {
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struct mpc_config_intsrc *irq = mp_irqs + idx;
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/* Do we already have a mapping for this ISA IRQ? */
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if (irq->mpc_srcbus == MP_ISA_BUS
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&& irq->mpc_srcbusirq == i)
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break;
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/* Do we already have a mapping for this IOAPIC pin */
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if ((irq->mpc_dstapic ==
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mp_irqs[mp_irq_entries].mpc_dstapic) &&
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(irq->mpc_dstirq == i))
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break;
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}
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if (idx != mp_irq_entries) {
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printk(KERN_DEBUG "ACPI: IRQ%d used by override.\n", i);
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continue; /* IRQ already used */
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}
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mp_irqs[mp_irq_entries].mpc_irqtype = mp_INT;
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mp_irqs[mp_irq_entries].mpc_srcbusirq = i; /* Identity mapped */
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mp_irqs[mp_irq_entries].mpc_dstirq = i;
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if (++mp_irq_entries == MAX_IRQ_SOURCES)
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panic("Max # of irq sources exceeded!!\n");
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}
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}
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int mp_register_gsi(u32 gsi, int triggering, int polarity)
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{
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int ioapic;
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int ioapic_pin;
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#ifdef CONFIG_X86_32
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#define MAX_GSI_NUM 4096
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#define IRQ_COMPRESSION_START 64
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static int pci_irq = IRQ_COMPRESSION_START;
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/*
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* Mapping between Global System Interrupts, which
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* represent all possible interrupts, and IRQs
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* assigned to actual devices.
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*/
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static int gsi_to_irq[MAX_GSI_NUM];
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#else
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if (acpi_irq_model != ACPI_IRQ_MODEL_IOAPIC)
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return gsi;
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#endif
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/* Don't set up the ACPI SCI because it's already set up */
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if (acpi_gbl_FADT.sci_interrupt == gsi)
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return gsi;
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ioapic = mp_find_ioapic(gsi);
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if (ioapic < 0) {
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printk(KERN_WARNING "No IOAPIC for GSI %u\n", gsi);
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return gsi;
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}
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ioapic_pin = gsi - mp_ioapic_routing[ioapic].gsi_base;
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#ifdef CONFIG_X86_32
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if (ioapic_renumber_irq)
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gsi = ioapic_renumber_irq(ioapic, gsi);
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#endif
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/*
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* Avoid pin reprogramming. PRTs typically include entries
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* with redundant pin->gsi mappings (but unique PCI devices);
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* we only program the IOAPIC on the first.
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*/
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if (ioapic_pin > MP_MAX_IOAPIC_PIN) {
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printk(KERN_ERR "Invalid reference to IOAPIC pin "
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"%d-%d\n", mp_ioapic_routing[ioapic].apic_id,
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ioapic_pin);
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return gsi;
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}
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if (test_bit(ioapic_pin, mp_ioapic_routing[ioapic].pin_programmed)) {
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Dprintk(KERN_DEBUG "Pin %d-%d already programmed\n",
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mp_ioapic_routing[ioapic].apic_id, ioapic_pin);
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#ifdef CONFIG_X86_32
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return (gsi < IRQ_COMPRESSION_START ? gsi : gsi_to_irq[gsi]);
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#else
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return gsi;
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#endif
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}
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set_bit(ioapic_pin, mp_ioapic_routing[ioapic].pin_programmed);
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#ifdef CONFIG_X86_32
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/*
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* For GSI >= 64, use IRQ compression
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*/
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if ((gsi >= IRQ_COMPRESSION_START)
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&& (triggering == ACPI_LEVEL_SENSITIVE)) {
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/*
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* For PCI devices assign IRQs in order, avoiding gaps
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* due to unused I/O APIC pins.
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*/
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int irq = gsi;
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if (gsi < MAX_GSI_NUM) {
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/*
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* Retain the VIA chipset work-around (gsi > 15), but
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* avoid a problem where the 8254 timer (IRQ0) is setup
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* via an override (so it's not on pin 0 of the ioapic),
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* and at the same time, the pin 0 interrupt is a PCI
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* type. The gsi > 15 test could cause these two pins
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* to be shared as IRQ0, and they are not shareable.
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* So test for this condition, and if necessary, avoid
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* the pin collision.
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*/
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gsi = pci_irq++;
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/*
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* Don't assign IRQ used by ACPI SCI
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*/
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if (gsi == acpi_gbl_FADT.sci_interrupt)
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gsi = pci_irq++;
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gsi_to_irq[irq] = gsi;
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} else {
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printk(KERN_ERR "GSI %u is too high\n", gsi);
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return gsi;
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}
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}
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#endif
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io_apic_set_pci_routing(ioapic, ioapic_pin, gsi,
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triggering == ACPI_EDGE_SENSITIVE ? 0 : 1,
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polarity == ACPI_ACTIVE_HIGH ? 0 : 1);
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return gsi;
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}
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/*
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* Parse IOAPIC related entries in MADT
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* returns 0 on success, < 0 on error
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@ -1,5 +1,5 @@
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/*
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2 * Intel Multiprocessor Specification 1.1 and 1.4
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* Intel Multiprocessor Specification 1.1 and 1.4
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* compliant MP-table parsing routines.
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*
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* (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
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@ -788,300 +788,3 @@ void __init find_smp_config(void)
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{
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__find_smp_config(1);
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}
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/* --------------------------------------------------------------------------
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ACPI-based MP Configuration
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-------------------------------------------------------------------------- */
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#ifdef CONFIG_ACPI
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#ifdef CONFIG_X86_IO_APIC
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#if defined(CONFIG_X86_ES7000) || defined(CONFIG_X86_GENERICARCH)
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extern int es7000_plat;
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#endif
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#define MP_ISA_BUS 0
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static struct mp_ioapic_routing mp_ioapic_routing[MAX_IO_APICS];
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static int mp_find_ioapic(int gsi)
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{
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int i = 0;
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/* Find the IOAPIC that manages this GSI. */
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for (i = 0; i < nr_ioapics; i++) {
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if ((gsi >= mp_ioapic_routing[i].gsi_base)
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&& (gsi <= mp_ioapic_routing[i].gsi_end))
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return i;
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}
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printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
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return -1;
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}
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static u8 __init uniq_ioapic_id(u8 id)
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{
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#ifdef CONFIG_X86_32
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if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
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!APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
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return io_apic_get_unique_id(nr_ioapics, id);
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else
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return id;
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#else
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int i;
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DECLARE_BITMAP(used, 256);
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bitmap_zero(used, 256);
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for (i = 0; i < nr_ioapics; i++) {
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struct mpc_config_ioapic *ia = &mp_ioapics[i];
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__set_bit(ia->mpc_apicid, used);
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}
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if (!test_bit(id, used))
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return id;
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return find_first_zero_bit(used, 256);
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#endif
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}
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void __init mp_register_ioapic(int id, u32 address, u32 gsi_base)
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{
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int idx = 0;
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if (bad_ioapic(address))
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return;
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idx = nr_ioapics;
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mp_ioapics[idx].mpc_type = MP_IOAPIC;
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mp_ioapics[idx].mpc_flags = MPC_APIC_USABLE;
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mp_ioapics[idx].mpc_apicaddr = address;
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set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
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mp_ioapics[idx].mpc_apicid = uniq_ioapic_id(id);
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#ifdef CONFIG_X86_32
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mp_ioapics[idx].mpc_apicver = io_apic_get_version(idx);
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#else
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mp_ioapics[idx].mpc_apicver = 0;
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#endif
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/*
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* Build basic GSI lookup table to facilitate gsi->io_apic lookups
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* and to prevent reprogramming of IOAPIC pins (PCI GSIs).
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*/
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mp_ioapic_routing[idx].apic_id = mp_ioapics[idx].mpc_apicid;
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mp_ioapic_routing[idx].gsi_base = gsi_base;
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mp_ioapic_routing[idx].gsi_end = gsi_base +
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io_apic_get_redir_entries(idx);
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printk(KERN_INFO "IOAPIC[%d]: apic_id %d, version %d, address 0x%x, "
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"GSI %d-%d\n", idx, mp_ioapics[idx].mpc_apicid,
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mp_ioapics[idx].mpc_apicver, mp_ioapics[idx].mpc_apicaddr,
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mp_ioapic_routing[idx].gsi_base, mp_ioapic_routing[idx].gsi_end);
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nr_ioapics++;
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}
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void __init mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger, u32 gsi)
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{
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struct mpc_config_intsrc intsrc;
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int ioapic = -1;
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int pin = -1;
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/*
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* Convert 'gsi' to 'ioapic.pin'.
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*/
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ioapic = mp_find_ioapic(gsi);
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if (ioapic < 0)
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return;
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pin = gsi - mp_ioapic_routing[ioapic].gsi_base;
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/*
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* TBD: This check is for faulty timer entries, where the override
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* erroneously sets the trigger to level, resulting in a HUGE
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* increase of timer interrupts!
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*/
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if ((bus_irq == 0) && (trigger == 3))
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trigger = 1;
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intsrc.mpc_type = MP_INTSRC;
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intsrc.mpc_irqtype = mp_INT;
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intsrc.mpc_irqflag = (trigger << 2) | polarity;
|
||||
intsrc.mpc_srcbus = MP_ISA_BUS;
|
||||
intsrc.mpc_srcbusirq = bus_irq; /* IRQ */
|
||||
intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; /* APIC ID */
|
||||
intsrc.mpc_dstirq = pin; /* INTIN# */
|
||||
|
||||
MP_intsrc_info(&intsrc);
|
||||
}
|
||||
|
||||
void __init mp_config_acpi_legacy_irqs(void)
|
||||
{
|
||||
struct mpc_config_intsrc intsrc;
|
||||
int i = 0;
|
||||
int ioapic = -1;
|
||||
|
||||
#if defined (CONFIG_MCA) || defined (CONFIG_EISA)
|
||||
/*
|
||||
* Fabricate the legacy ISA bus (bus #31).
|
||||
*/
|
||||
mp_bus_id_to_type[MP_ISA_BUS] = MP_BUS_ISA;
|
||||
#endif
|
||||
set_bit(MP_ISA_BUS, mp_bus_not_pci);
|
||||
Dprintk("Bus #%d is ISA\n", MP_ISA_BUS);
|
||||
|
||||
#if defined(CONFIG_X86_ES7000) || defined(CONFIG_X86_GENERICARCH)
|
||||
/*
|
||||
* Older generations of ES7000 have no legacy identity mappings
|
||||
*/
|
||||
if (es7000_plat == 1)
|
||||
return;
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Locate the IOAPIC that manages the ISA IRQs (0-15).
|
||||
*/
|
||||
ioapic = mp_find_ioapic(0);
|
||||
if (ioapic < 0)
|
||||
return;
|
||||
|
||||
intsrc.mpc_type = MP_INTSRC;
|
||||
intsrc.mpc_irqflag = 0; /* Conforming */
|
||||
intsrc.mpc_srcbus = MP_ISA_BUS;
|
||||
#ifdef CONFIG_X86_IO_APIC
|
||||
intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid;
|
||||
#endif
|
||||
/*
|
||||
* Use the default configuration for the IRQs 0-15. Unless
|
||||
* overridden by (MADT) interrupt source override entries.
|
||||
*/
|
||||
for (i = 0; i < 16; i++) {
|
||||
int idx;
|
||||
|
||||
for (idx = 0; idx < mp_irq_entries; idx++) {
|
||||
struct mpc_config_intsrc *irq = mp_irqs + idx;
|
||||
|
||||
/* Do we already have a mapping for this ISA IRQ? */
|
||||
if (irq->mpc_srcbus == MP_ISA_BUS
|
||||
&& irq->mpc_srcbusirq == i)
|
||||
break;
|
||||
|
||||
/* Do we already have a mapping for this IOAPIC pin */
|
||||
if ((irq->mpc_dstapic == intsrc.mpc_dstapic) &&
|
||||
(irq->mpc_dstirq == i))
|
||||
break;
|
||||
}
|
||||
|
||||
if (idx != mp_irq_entries) {
|
||||
printk(KERN_DEBUG "ACPI: IRQ%d used by override.\n", i);
|
||||
continue; /* IRQ already used */
|
||||
}
|
||||
|
||||
intsrc.mpc_irqtype = mp_INT;
|
||||
intsrc.mpc_srcbusirq = i; /* Identity mapped */
|
||||
intsrc.mpc_dstirq = i;
|
||||
|
||||
MP_intsrc_info(&intsrc);
|
||||
}
|
||||
}
|
||||
|
||||
int mp_register_gsi(u32 gsi, int triggering, int polarity)
|
||||
{
|
||||
int ioapic;
|
||||
int ioapic_pin;
|
||||
#ifdef CONFIG_X86_32
|
||||
#define MAX_GSI_NUM 4096
|
||||
#define IRQ_COMPRESSION_START 64
|
||||
|
||||
static int pci_irq = IRQ_COMPRESSION_START;
|
||||
/*
|
||||
* Mapping between Global System Interrupts, which
|
||||
* represent all possible interrupts, and IRQs
|
||||
* assigned to actual devices.
|
||||
*/
|
||||
static int gsi_to_irq[MAX_GSI_NUM];
|
||||
#else
|
||||
|
||||
if (acpi_irq_model != ACPI_IRQ_MODEL_IOAPIC)
|
||||
return gsi;
|
||||
#endif
|
||||
|
||||
/* Don't set up the ACPI SCI because it's already set up */
|
||||
if (acpi_gbl_FADT.sci_interrupt == gsi)
|
||||
return gsi;
|
||||
|
||||
ioapic = mp_find_ioapic(gsi);
|
||||
if (ioapic < 0) {
|
||||
printk(KERN_WARNING "No IOAPIC for GSI %u\n", gsi);
|
||||
return gsi;
|
||||
}
|
||||
|
||||
ioapic_pin = gsi - mp_ioapic_routing[ioapic].gsi_base;
|
||||
|
||||
#ifdef CONFIG_X86_32
|
||||
if (ioapic_renumber_irq)
|
||||
gsi = ioapic_renumber_irq(ioapic, gsi);
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Avoid pin reprogramming. PRTs typically include entries
|
||||
* with redundant pin->gsi mappings (but unique PCI devices);
|
||||
* we only program the IOAPIC on the first.
|
||||
*/
|
||||
if (ioapic_pin > MP_MAX_IOAPIC_PIN) {
|
||||
printk(KERN_ERR "Invalid reference to IOAPIC pin "
|
||||
"%d-%d\n", mp_ioapic_routing[ioapic].apic_id,
|
||||
ioapic_pin);
|
||||
return gsi;
|
||||
}
|
||||
if (test_bit(ioapic_pin, mp_ioapic_routing[ioapic].pin_programmed)) {
|
||||
Dprintk(KERN_DEBUG "Pin %d-%d already programmed\n",
|
||||
mp_ioapic_routing[ioapic].apic_id, ioapic_pin);
|
||||
#ifdef CONFIG_X86_32
|
||||
return (gsi < IRQ_COMPRESSION_START ? gsi : gsi_to_irq[gsi]);
|
||||
#else
|
||||
return gsi;
|
||||
#endif
|
||||
}
|
||||
|
||||
set_bit(ioapic_pin, mp_ioapic_routing[ioapic].pin_programmed);
|
||||
#ifdef CONFIG_X86_32
|
||||
/*
|
||||
* For GSI >= 64, use IRQ compression
|
||||
*/
|
||||
if ((gsi >= IRQ_COMPRESSION_START)
|
||||
&& (triggering == ACPI_LEVEL_SENSITIVE)) {
|
||||
/*
|
||||
* For PCI devices assign IRQs in order, avoiding gaps
|
||||
* due to unused I/O APIC pins.
|
||||
*/
|
||||
int irq = gsi;
|
||||
if (gsi < MAX_GSI_NUM) {
|
||||
/*
|
||||
* Retain the VIA chipset work-around (gsi > 15), but
|
||||
* avoid a problem where the 8254 timer (IRQ0) is setup
|
||||
* via an override (so it's not on pin 0 of the ioapic),
|
||||
* and at the same time, the pin 0 interrupt is a PCI
|
||||
* type. The gsi > 15 test could cause these two pins
|
||||
* to be shared as IRQ0, and they are not shareable.
|
||||
* So test for this condition, and if necessary, avoid
|
||||
* the pin collision.
|
||||
*/
|
||||
gsi = pci_irq++;
|
||||
/*
|
||||
* Don't assign IRQ used by ACPI SCI
|
||||
*/
|
||||
if (gsi == acpi_gbl_FADT.sci_interrupt)
|
||||
gsi = pci_irq++;
|
||||
gsi_to_irq[irq] = gsi;
|
||||
} else {
|
||||
printk(KERN_ERR "GSI %u is too high\n", gsi);
|
||||
return gsi;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
io_apic_set_pci_routing(ioapic, ioapic_pin, gsi,
|
||||
triggering == ACPI_EDGE_SENSITIVE ? 0 : 1,
|
||||
polarity == ACPI_ACTIVE_HIGH ? 0 : 1);
|
||||
return gsi;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_X86_IO_APIC */
|
||||
#endif /* CONFIG_ACPI */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user