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drm/amd/display: add getter routine to retrieve mpcc mux

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[Why & How]
Add function to identify which MPCC is providing input to a specified OPP

Signed-off-by: Josip Pavic <Josip.Pavic@amd.com>
Acked-by: Bindu Ramamurthy <bindu.r@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Josip Pavic 2020-12-11 00:09:11 -05:00 committed by Alex Deucher
parent 4aa9d658d2
commit 110b055b28
5 changed files with 19 additions and 0 deletions
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12
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
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@ -467,6 +467,17 @@ void mpc1_cursor_lock(struct mpc *mpc, int opp_id, bool lock)
REG_SET(CUR[opp_id], 0, CUR_VUPDATE_LOCK_SET, lock ? 1 : 0); REG_SET(CUR[opp_id], 0, CUR_VUPDATE_LOCK_SET, lock ? 1 : 0);
} }
unsigned int mpc1_get_mpc_out_mux(struct mpc *mpc, int opp_id)
{
struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
uint32_t val;
if (opp_id < MAX_OPP && REG(MUX[opp_id]))
REG_GET(MUX[opp_id], MPC_OUT_MUX, &val);
return val;
}
static const struct mpc_funcs dcn10_mpc_funcs = { static const struct mpc_funcs dcn10_mpc_funcs = {
.read_mpcc_state = mpc1_read_mpcc_state, .read_mpcc_state = mpc1_read_mpcc_state,
.insert_plane = mpc1_insert_plane, .insert_plane = mpc1_insert_plane,
@ -483,6 +494,7 @@ static const struct mpc_funcs dcn10_mpc_funcs = {
.set_denorm_clamp = NULL, .set_denorm_clamp = NULL,
.set_output_csc = NULL, .set_output_csc = NULL,
.set_output_gamma = NULL, .set_output_gamma = NULL,
.get_mpc_out_mux = mpc1_get_mpc_out_mux,
}; };
void dcn10_mpc_construct(struct dcn10_mpc *mpc10, void dcn10_mpc_construct(struct dcn10_mpc *mpc10,

1
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h
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@ -200,4 +200,5 @@ void mpc1_read_mpcc_state(
void mpc1_cursor_lock(struct mpc *mpc, int opp_id, bool lock); void mpc1_cursor_lock(struct mpc *mpc, int opp_id, bool lock);
unsigned int mpc1_get_mpc_out_mux(struct mpc *mpc, int opp_id);
#endif #endif

1
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c
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@ -556,6 +556,7 @@ const struct mpc_funcs dcn20_mpc_funcs = {
.set_ocsc_default = mpc2_set_ocsc_default, .set_ocsc_default = mpc2_set_ocsc_default,
.set_output_gamma = mpc2_set_output_gamma, .set_output_gamma = mpc2_set_output_gamma,
.power_on_mpc_mem_pwr = mpc20_power_on_ogam_lut, .power_on_mpc_mem_pwr = mpc20_power_on_ogam_lut,
.get_mpc_out_mux = mpc1_get_mpc_out_mux,
}; };
void dcn20_mpc_construct(struct dcn20_mpc *mpc20, void dcn20_mpc_construct(struct dcn20_mpc *mpc20,

1
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c
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@ -1428,6 +1428,7 @@ const struct mpc_funcs dcn30_mpc_funcs = {
.program_3dlut = mpc3_program_3dlut, .program_3dlut = mpc3_program_3dlut,
.release_rmu = mpcc3_release_rmu, .release_rmu = mpcc3_release_rmu,
.power_on_mpc_mem_pwr = mpc20_power_on_ogam_lut, .power_on_mpc_mem_pwr = mpc20_power_on_ogam_lut,
.get_mpc_out_mux = mpc1_get_mpc_out_mux,
}; };

4
drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
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@ -359,6 +359,10 @@ struct mpc_funcs {
int (*release_rmu)(struct mpc *mpc, int mpcc_id); int (*release_rmu)(struct mpc *mpc, int mpcc_id);
unsigned int (*get_mpc_out_mux)(
struct mpc *mpc,
int opp_id);
}; };
#endif #endif