forked from Minki/linux
drm/radeon: clean up sumo_rlc_init() for code sharing
This will eventually be shared with newer asics to reduce code duplication. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher
parent
866d83de0c
commit
10b7ca7e09
@ -3910,131 +3910,136 @@ int sumo_rlc_init(struct radeon_device *rdev)
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dws = rdev->rlc.reg_list_size;
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cs_data = rdev->rlc.cs_data;
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/* save restore block */
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if (rdev->rlc.save_restore_obj == NULL) {
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r = radeon_bo_create(rdev, dws * 4, PAGE_SIZE, true,
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RADEON_GEM_DOMAIN_VRAM, NULL, &rdev->rlc.save_restore_obj);
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if (r) {
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dev_warn(rdev->dev, "(%d) create RLC sr bo failed\n", r);
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return r;
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if (src_ptr) {
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/* save restore block */
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if (rdev->rlc.save_restore_obj == NULL) {
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r = radeon_bo_create(rdev, dws * 4, PAGE_SIZE, true,
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RADEON_GEM_DOMAIN_VRAM, NULL, &rdev->rlc.save_restore_obj);
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if (r) {
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dev_warn(rdev->dev, "(%d) create RLC sr bo failed\n", r);
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return r;
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}
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}
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}
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r = radeon_bo_reserve(rdev->rlc.save_restore_obj, false);
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if (unlikely(r != 0)) {
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sumo_rlc_fini(rdev);
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return r;
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}
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r = radeon_bo_pin(rdev->rlc.save_restore_obj, RADEON_GEM_DOMAIN_VRAM,
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&rdev->rlc.save_restore_gpu_addr);
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if (r) {
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radeon_bo_unreserve(rdev->rlc.save_restore_obj);
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dev_warn(rdev->dev, "(%d) pin RLC sr bo failed\n", r);
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sumo_rlc_fini(rdev);
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return r;
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}
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r = radeon_bo_kmap(rdev->rlc.save_restore_obj, (void **)&rdev->rlc.sr_ptr);
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if (r) {
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dev_warn(rdev->dev, "(%d) map RLC sr bo failed\n", r);
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sumo_rlc_fini(rdev);
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return r;
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}
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/* write the sr buffer */
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dst_ptr = rdev->rlc.sr_ptr;
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/* format:
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* dw0: (reg2 << 16) | reg1
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* dw1: reg1 save space
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* dw2: reg2 save space
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*/
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for (i = 0; i < dws; i++) {
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data = src_ptr[i] >> 2;
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i++;
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if (i < dws)
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data |= (src_ptr[i] >> 2) << 16;
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j = (((i - 1) * 3) / 2);
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dst_ptr[j] = data;
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}
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j = ((i * 3) / 2);
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dst_ptr[j] = RLC_SAVE_RESTORE_LIST_END_MARKER;
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radeon_bo_kunmap(rdev->rlc.save_restore_obj);
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radeon_bo_unreserve(rdev->rlc.save_restore_obj);
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/* clear state block */
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reg_list_num = 0;
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dws = 0;
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for (i = 0; cs_data[i].section != NULL; i++) {
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for (j = 0; cs_data[i].section[j].extent != NULL; j++) {
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reg_list_num++;
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dws += cs_data[i].section[j].reg_count;
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}
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}
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reg_list_blk_index = (3 * reg_list_num + 2);
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dws += reg_list_blk_index;
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if (rdev->rlc.clear_state_obj == NULL) {
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r = radeon_bo_create(rdev, dws * 4, PAGE_SIZE, true,
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RADEON_GEM_DOMAIN_VRAM, NULL, &rdev->rlc.clear_state_obj);
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if (r) {
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dev_warn(rdev->dev, "(%d) create RLC c bo failed\n", r);
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r = radeon_bo_reserve(rdev->rlc.save_restore_obj, false);
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if (unlikely(r != 0)) {
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sumo_rlc_fini(rdev);
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return r;
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}
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}
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r = radeon_bo_reserve(rdev->rlc.clear_state_obj, false);
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if (unlikely(r != 0)) {
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sumo_rlc_fini(rdev);
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return r;
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}
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r = radeon_bo_pin(rdev->rlc.clear_state_obj, RADEON_GEM_DOMAIN_VRAM,
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&rdev->rlc.clear_state_gpu_addr);
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if (r) {
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radeon_bo_unreserve(rdev->rlc.clear_state_obj);
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dev_warn(rdev->dev, "(%d) pin RLC c bo failed\n", r);
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sumo_rlc_fini(rdev);
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return r;
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}
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r = radeon_bo_kmap(rdev->rlc.clear_state_obj, (void **)&rdev->rlc.cs_ptr);
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if (r) {
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dev_warn(rdev->dev, "(%d) map RLC c bo failed\n", r);
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sumo_rlc_fini(rdev);
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return r;
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}
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/* set up the cs buffer */
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dst_ptr = rdev->rlc.cs_ptr;
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reg_list_hdr_blk_index = 0;
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reg_list_mc_addr = rdev->rlc.clear_state_gpu_addr + (reg_list_blk_index * 4);
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data = upper_32_bits(reg_list_mc_addr);
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dst_ptr[reg_list_hdr_blk_index] = data;
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reg_list_hdr_blk_index++;
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for (i = 0; cs_data[i].section != NULL; i++) {
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for (j = 0; cs_data[i].section[j].extent != NULL; j++) {
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reg_num = cs_data[i].section[j].reg_count;
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data = reg_list_mc_addr & 0xffffffff;
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dst_ptr[reg_list_hdr_blk_index] = data;
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reg_list_hdr_blk_index++;
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data = (cs_data[i].section[j].reg_index * 4) & 0xffffffff;
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dst_ptr[reg_list_hdr_blk_index] = data;
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reg_list_hdr_blk_index++;
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data = 0x08000000 | (reg_num * 4);
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dst_ptr[reg_list_hdr_blk_index] = data;
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reg_list_hdr_blk_index++;
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for (k = 0; k < reg_num; k++) {
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data = cs_data[i].section[j].extent[k];
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dst_ptr[reg_list_blk_index + k] = data;
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}
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reg_list_mc_addr += reg_num * 4;
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reg_list_blk_index += reg_num;
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r = radeon_bo_pin(rdev->rlc.save_restore_obj, RADEON_GEM_DOMAIN_VRAM,
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&rdev->rlc.save_restore_gpu_addr);
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if (r) {
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radeon_bo_unreserve(rdev->rlc.save_restore_obj);
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dev_warn(rdev->dev, "(%d) pin RLC sr bo failed\n", r);
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sumo_rlc_fini(rdev);
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return r;
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}
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}
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dst_ptr[reg_list_hdr_blk_index] = RLC_CLEAR_STATE_END_MARKER;
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radeon_bo_kunmap(rdev->rlc.clear_state_obj);
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radeon_bo_unreserve(rdev->rlc.clear_state_obj);
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r = radeon_bo_kmap(rdev->rlc.save_restore_obj, (void **)&rdev->rlc.sr_ptr);
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if (r) {
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dev_warn(rdev->dev, "(%d) map RLC sr bo failed\n", r);
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sumo_rlc_fini(rdev);
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return r;
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}
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/* write the sr buffer */
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dst_ptr = rdev->rlc.sr_ptr;
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/* format:
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* dw0: (reg2 << 16) | reg1
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* dw1: reg1 save space
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* dw2: reg2 save space
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*/
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for (i = 0; i < dws; i++) {
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data = src_ptr[i] >> 2;
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i++;
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if (i < dws)
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data |= (src_ptr[i] >> 2) << 16;
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j = (((i - 1) * 3) / 2);
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dst_ptr[j] = data;
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}
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j = ((i * 3) / 2);
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dst_ptr[j] = RLC_SAVE_RESTORE_LIST_END_MARKER;
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radeon_bo_kunmap(rdev->rlc.save_restore_obj);
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radeon_bo_unreserve(rdev->rlc.save_restore_obj);
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}
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if (cs_data) {
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/* clear state block */
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reg_list_num = 0;
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dws = 0;
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for (i = 0; cs_data[i].section != NULL; i++) {
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for (j = 0; cs_data[i].section[j].extent != NULL; j++) {
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reg_list_num++;
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dws += cs_data[i].section[j].reg_count;
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}
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}
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reg_list_blk_index = (3 * reg_list_num + 2);
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dws += reg_list_blk_index;
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if (rdev->rlc.clear_state_obj == NULL) {
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r = radeon_bo_create(rdev, dws * 4, PAGE_SIZE, true,
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RADEON_GEM_DOMAIN_VRAM, NULL, &rdev->rlc.clear_state_obj);
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if (r) {
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dev_warn(rdev->dev, "(%d) create RLC c bo failed\n", r);
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sumo_rlc_fini(rdev);
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return r;
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}
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}
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r = radeon_bo_reserve(rdev->rlc.clear_state_obj, false);
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if (unlikely(r != 0)) {
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sumo_rlc_fini(rdev);
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return r;
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}
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r = radeon_bo_pin(rdev->rlc.clear_state_obj, RADEON_GEM_DOMAIN_VRAM,
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&rdev->rlc.clear_state_gpu_addr);
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if (r) {
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radeon_bo_unreserve(rdev->rlc.clear_state_obj);
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dev_warn(rdev->dev, "(%d) pin RLC c bo failed\n", r);
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sumo_rlc_fini(rdev);
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return r;
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}
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r = radeon_bo_kmap(rdev->rlc.clear_state_obj, (void **)&rdev->rlc.cs_ptr);
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if (r) {
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dev_warn(rdev->dev, "(%d) map RLC c bo failed\n", r);
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sumo_rlc_fini(rdev);
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return r;
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}
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/* set up the cs buffer */
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dst_ptr = rdev->rlc.cs_ptr;
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reg_list_hdr_blk_index = 0;
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reg_list_mc_addr = rdev->rlc.clear_state_gpu_addr + (reg_list_blk_index * 4);
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data = upper_32_bits(reg_list_mc_addr);
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dst_ptr[reg_list_hdr_blk_index] = data;
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reg_list_hdr_blk_index++;
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for (i = 0; cs_data[i].section != NULL; i++) {
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for (j = 0; cs_data[i].section[j].extent != NULL; j++) {
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reg_num = cs_data[i].section[j].reg_count;
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data = reg_list_mc_addr & 0xffffffff;
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dst_ptr[reg_list_hdr_blk_index] = data;
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reg_list_hdr_blk_index++;
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data = (cs_data[i].section[j].reg_index * 4) & 0xffffffff;
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dst_ptr[reg_list_hdr_blk_index] = data;
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reg_list_hdr_blk_index++;
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data = 0x08000000 | (reg_num * 4);
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dst_ptr[reg_list_hdr_blk_index] = data;
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reg_list_hdr_blk_index++;
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for (k = 0; k < reg_num; k++) {
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data = cs_data[i].section[j].extent[k];
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dst_ptr[reg_list_blk_index + k] = data;
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}
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reg_list_mc_addr += reg_num * 4;
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reg_list_blk_index += reg_num;
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}
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}
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dst_ptr[reg_list_hdr_blk_index] = RLC_CLEAR_STATE_END_MARKER;
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radeon_bo_kunmap(rdev->rlc.clear_state_obj);
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radeon_bo_unreserve(rdev->rlc.clear_state_obj);
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}
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return 0;
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}
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