forked from Minki/linux
crypto: aspeed - Add HACE hash driver
Hash and Crypto Engine (HACE) is designed to accelerate the throughput of hash data digest, encryption, and decryption. Basically, HACE can be divided into two independently engines - Hash Engine and Crypto Engine. This patch aims to add HACE hash engine driver for hash accelerator. Signed-off-by: Neal Liu <neal_liu@aspeedtech.com> Signed-off-by: Johnny Huang <johnny_huang@aspeedtech.com> Reviewed-by: Dhananjay Phadke <dphadke@linux.microsoft.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This commit is contained in:
Neal Liu
Herbert Xu
parent
efb4b01c1c
commit
108713a713
@ -3210,6 +3210,13 @@ S: Maintained
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F: Documentation/devicetree/bindings/usb/aspeed,ast2600-udc.yaml
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F: drivers/usb/gadget/udc/aspeed_udc.c
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ASPEED CRYPTO DRIVER
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M: Neal Liu <neal_liu@aspeedtech.com>
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L: linux-aspeed@lists.ozlabs.org (moderated for non-subscribers)
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S: Maintained
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F: Documentation/devicetree/bindings/crypto/aspeed,ast2500-hace.yaml
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F: drivers/crypto/aspeed/
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ASUS NOTEBOOKS AND EEEPC ACPI/WMI EXTRAS DRIVERS
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M: Corentin Chary <corentin.chary@gmail.com>
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L: acpi4asus-user@lists.sourceforge.net
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@ -818,5 +818,6 @@ config CRYPTO_DEV_SA2UL
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acceleration for cryptographic algorithms on these devices.
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source "drivers/crypto/keembay/Kconfig"
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source "drivers/crypto/aspeed/Kconfig"
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endif # CRYPTO_HW
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@ -1,5 +1,6 @@
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# SPDX-License-Identifier: GPL-2.0
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obj-$(CONFIG_CRYPTO_DEV_ALLWINNER) += allwinner/
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obj-$(CONFIG_CRYPTO_DEV_ASPEED) += aspeed/
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obj-$(CONFIG_CRYPTO_DEV_ATMEL_AES) += atmel-aes.o
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obj-$(CONFIG_CRYPTO_DEV_ATMEL_SHA) += atmel-sha.o
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obj-$(CONFIG_CRYPTO_DEV_ATMEL_TDES) += atmel-tdes.o
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32
drivers/crypto/aspeed/Kconfig
Normal file
32
drivers/crypto/aspeed/Kconfig
Normal file
@ -0,0 +1,32 @@
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config CRYPTO_DEV_ASPEED
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tristate "Support for Aspeed cryptographic engine driver"
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depends on ARCH_ASPEED
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help
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Hash and Crypto Engine (HACE) is designed to accelerate the
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throughput of hash data digest, encryption and decryption.
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Select y here to have support for the cryptographic driver
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available on Aspeed SoC.
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config CRYPTO_DEV_ASPEED_DEBUG
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bool "Enable Aspeed crypto debug messages"
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depends on CRYPTO_DEV_ASPEED
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help
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Print Aspeed crypto debugging messages if you use this
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option to ask for those messages.
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Avoid enabling this option for production build to
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minimize driver timing.
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config CRYPTO_DEV_ASPEED_HACE_HASH
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bool "Enable Aspeed Hash & Crypto Engine (HACE) hash"
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depends on CRYPTO_DEV_ASPEED
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select CRYPTO_ENGINE
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select CRYPTO_SHA1
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select CRYPTO_SHA256
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select CRYPTO_SHA512
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select CRYPTO_HMAC
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help
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Select here to enable Aspeed Hash & Crypto Engine (HACE)
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hash driver.
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Supports multiple message digest standards, including
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SHA-1, SHA-224, SHA-256, SHA-384, SHA-512, and so on.
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6
drivers/crypto/aspeed/Makefile
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6
drivers/crypto/aspeed/Makefile
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@ -0,0 +1,6 @@
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obj-$(CONFIG_CRYPTO_DEV_ASPEED) += aspeed_crypto.o
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aspeed_crypto-objs := aspeed-hace.o \
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$(hace-hash-y)
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obj-$(CONFIG_CRYPTO_DEV_ASPEED_HACE_HASH) += aspeed-hace-hash.o
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hace-hash-$(CONFIG_CRYPTO_DEV_ASPEED_HACE_HASH) := aspeed-hace-hash.o
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1389
drivers/crypto/aspeed/aspeed-hace-hash.c
Normal file
1389
drivers/crypto/aspeed/aspeed-hace-hash.c
Normal file
File diff suppressed because it is too large
Load Diff
206
drivers/crypto/aspeed/aspeed-hace.c
Normal file
206
drivers/crypto/aspeed/aspeed-hace.c
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@ -0,0 +1,206 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2021 Aspeed Technology Inc.
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*/
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#include <linux/clk.h>
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#include <linux/module.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/of_irq.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include "aspeed-hace.h"
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#ifdef CONFIG_CRYPTO_DEV_ASPEED_DEBUG
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#define HACE_DBG(d, fmt, ...) \
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dev_info((d)->dev, "%s() " fmt, __func__, ##__VA_ARGS__)
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#else
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#define HACE_DBG(d, fmt, ...) \
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dev_dbg((d)->dev, "%s() " fmt, __func__, ##__VA_ARGS__)
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#endif
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/* HACE interrupt service routine */
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static irqreturn_t aspeed_hace_irq(int irq, void *dev)
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{
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struct aspeed_hace_dev *hace_dev = (struct aspeed_hace_dev *)dev;
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struct aspeed_engine_hash *hash_engine = &hace_dev->hash_engine;
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u32 sts;
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sts = ast_hace_read(hace_dev, ASPEED_HACE_STS);
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ast_hace_write(hace_dev, sts, ASPEED_HACE_STS);
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HACE_DBG(hace_dev, "irq status: 0x%x\n", sts);
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if (sts & HACE_HASH_ISR) {
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if (hash_engine->flags & CRYPTO_FLAGS_BUSY)
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tasklet_schedule(&hash_engine->done_task);
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else
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dev_warn(hace_dev->dev, "HASH no active requests.\n");
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}
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return IRQ_HANDLED;
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}
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static void aspeed_hace_hash_done_task(unsigned long data)
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{
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struct aspeed_hace_dev *hace_dev = (struct aspeed_hace_dev *)data;
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struct aspeed_engine_hash *hash_engine = &hace_dev->hash_engine;
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hash_engine->resume(hace_dev);
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}
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static void aspeed_hace_register(struct aspeed_hace_dev *hace_dev)
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{
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#ifdef CONFIG_CRYPTO_DEV_ASPEED_HACE_HASH
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aspeed_register_hace_hash_algs(hace_dev);
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#endif
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}
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static void aspeed_hace_unregister(struct aspeed_hace_dev *hace_dev)
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{
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#ifdef CONFIG_CRYPTO_DEV_ASPEED_HACE_HASH
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aspeed_unregister_hace_hash_algs(hace_dev);
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#endif
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}
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static const struct of_device_id aspeed_hace_of_matches[] = {
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{ .compatible = "aspeed,ast2500-hace", .data = (void *)5, },
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{ .compatible = "aspeed,ast2600-hace", .data = (void *)6, },
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{},
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};
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static int aspeed_hace_probe(struct platform_device *pdev)
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{
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const struct of_device_id *hace_dev_id;
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struct aspeed_engine_hash *hash_engine;
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struct aspeed_hace_dev *hace_dev;
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struct resource *res;
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int rc;
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hace_dev = devm_kzalloc(&pdev->dev, sizeof(struct aspeed_hace_dev),
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GFP_KERNEL);
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if (!hace_dev)
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return -ENOMEM;
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hace_dev_id = of_match_device(aspeed_hace_of_matches, &pdev->dev);
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if (!hace_dev_id) {
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dev_err(&pdev->dev, "Failed to match hace dev id\n");
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return -EINVAL;
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}
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hace_dev->dev = &pdev->dev;
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hace_dev->version = (unsigned long)hace_dev_id->data;
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hash_engine = &hace_dev->hash_engine;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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platform_set_drvdata(pdev, hace_dev);
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hace_dev->regs = devm_ioremap_resource(&pdev->dev, res);
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if (!hace_dev->regs) {
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dev_err(&pdev->dev, "Failed to map resources\n");
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return -ENOMEM;
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}
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/* Get irq number and register it */
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hace_dev->irq = platform_get_irq(pdev, 0);
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if (!hace_dev->irq) {
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dev_err(&pdev->dev, "Failed to get interrupt\n");
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return -ENXIO;
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}
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rc = devm_request_irq(&pdev->dev, hace_dev->irq, aspeed_hace_irq, 0,
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dev_name(&pdev->dev), hace_dev);
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if (rc) {
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dev_err(&pdev->dev, "Failed to request interrupt\n");
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return rc;
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}
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/* Get clk and enable it */
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hace_dev->clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(hace_dev->clk)) {
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dev_err(&pdev->dev, "Failed to get clk\n");
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return -ENODEV;
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}
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rc = clk_prepare_enable(hace_dev->clk);
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if (rc) {
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dev_err(&pdev->dev, "Failed to enable clock 0x%x\n", rc);
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return rc;
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}
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/* Initialize crypto hardware engine structure for hash */
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hace_dev->crypt_engine_hash = crypto_engine_alloc_init(hace_dev->dev,
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true);
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if (!hace_dev->crypt_engine_hash) {
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rc = -ENOMEM;
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goto clk_exit;
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}
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rc = crypto_engine_start(hace_dev->crypt_engine_hash);
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if (rc)
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goto err_engine_hash_start;
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tasklet_init(&hash_engine->done_task, aspeed_hace_hash_done_task,
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(unsigned long)hace_dev);
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/* Allocate DMA buffer for hash engine input used */
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hash_engine->ahash_src_addr =
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dmam_alloc_coherent(&pdev->dev,
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ASPEED_HASH_SRC_DMA_BUF_LEN,
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&hash_engine->ahash_src_dma_addr,
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GFP_KERNEL);
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if (!hash_engine->ahash_src_addr) {
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dev_err(&pdev->dev, "Failed to allocate dma buffer\n");
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rc = -ENOMEM;
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goto err_engine_hash_start;
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}
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aspeed_hace_register(hace_dev);
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dev_info(&pdev->dev, "Aspeed Crypto Accelerator successfully registered\n");
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return 0;
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err_engine_hash_start:
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crypto_engine_exit(hace_dev->crypt_engine_hash);
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clk_exit:
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clk_disable_unprepare(hace_dev->clk);
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return rc;
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}
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static int aspeed_hace_remove(struct platform_device *pdev)
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{
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struct aspeed_hace_dev *hace_dev = platform_get_drvdata(pdev);
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struct aspeed_engine_hash *hash_engine = &hace_dev->hash_engine;
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aspeed_hace_unregister(hace_dev);
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crypto_engine_exit(hace_dev->crypt_engine_hash);
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tasklet_kill(&hash_engine->done_task);
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clk_disable_unprepare(hace_dev->clk);
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return 0;
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}
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MODULE_DEVICE_TABLE(of, aspeed_hace_of_matches);
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static struct platform_driver aspeed_hace_driver = {
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.probe = aspeed_hace_probe,
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.remove = aspeed_hace_remove,
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.driver = {
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.name = KBUILD_MODNAME,
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.of_match_table = aspeed_hace_of_matches,
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},
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};
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module_platform_driver(aspeed_hace_driver);
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MODULE_AUTHOR("Neal Liu <neal_liu@aspeedtech.com>");
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MODULE_DESCRIPTION("Aspeed HACE driver Crypto Accelerator");
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MODULE_LICENSE("GPL");
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186
drivers/crypto/aspeed/aspeed-hace.h
Normal file
186
drivers/crypto/aspeed/aspeed-hace.h
Normal file
@ -0,0 +1,186 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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#ifndef __ASPEED_HACE_H__
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#define __ASPEED_HACE_H__
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#include <linux/interrupt.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/fips.h>
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#include <linux/dma-mapping.h>
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#include <crypto/scatterwalk.h>
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#include <crypto/internal/aead.h>
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#include <crypto/internal/akcipher.h>
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#include <crypto/internal/hash.h>
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#include <crypto/internal/kpp.h>
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#include <crypto/internal/skcipher.h>
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#include <crypto/algapi.h>
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#include <crypto/engine.h>
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#include <crypto/hmac.h>
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#include <crypto/sha1.h>
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#include <crypto/sha2.h>
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/*****************************
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* *
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* HACE register definitions *
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* *
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* ***************************/
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#define ASPEED_HACE_STS 0x1C /* HACE Status Register */
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#define ASPEED_HACE_HASH_SRC 0x20 /* Hash Data Source Base Address Register */
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#define ASPEED_HACE_HASH_DIGEST_BUFF 0x24 /* Hash Digest Write Buffer Base Address Register */
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#define ASPEED_HACE_HASH_KEY_BUFF 0x28 /* Hash HMAC Key Buffer Base Address Register */
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#define ASPEED_HACE_HASH_DATA_LEN 0x2C /* Hash Data Length Register */
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#define ASPEED_HACE_HASH_CMD 0x30 /* Hash Engine Command Register */
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/* interrupt status reg */
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#define HACE_HASH_ISR BIT(9)
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#define HACE_HASH_BUSY BIT(0)
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/* hash cmd reg */
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#define HASH_CMD_MBUS_REQ_SYNC_EN BIT(20)
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#define HASH_CMD_HASH_SRC_SG_CTRL BIT(18)
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#define HASH_CMD_SHA512_224 (0x3 << 10)
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#define HASH_CMD_SHA512_256 (0x2 << 10)
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#define HASH_CMD_SHA384 (0x1 << 10)
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#define HASH_CMD_SHA512 (0)
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#define HASH_CMD_INT_ENABLE BIT(9)
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#define HASH_CMD_HMAC (0x1 << 7)
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#define HASH_CMD_ACC_MODE (0x2 << 7)
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#define HASH_CMD_HMAC_KEY (0x3 << 7)
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#define HASH_CMD_SHA1 (0x2 << 4)
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#define HASH_CMD_SHA224 (0x4 << 4)
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#define HASH_CMD_SHA256 (0x5 << 4)
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#define HASH_CMD_SHA512_SER (0x6 << 4)
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#define HASH_CMD_SHA_SWAP (0x2 << 2)
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#define HASH_SG_LAST_LIST BIT(31)
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#define CRYPTO_FLAGS_BUSY BIT(1)
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#define SHA_OP_UPDATE 1
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#define SHA_OP_FINAL 2
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#define SHA_FLAGS_SHA1 BIT(0)
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#define SHA_FLAGS_SHA224 BIT(1)
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#define SHA_FLAGS_SHA256 BIT(2)
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#define SHA_FLAGS_SHA384 BIT(3)
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#define SHA_FLAGS_SHA512 BIT(4)
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#define SHA_FLAGS_SHA512_224 BIT(5)
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#define SHA_FLAGS_SHA512_256 BIT(6)
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#define SHA_FLAGS_HMAC BIT(8)
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#define SHA_FLAGS_FINUP BIT(9)
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#define SHA_FLAGS_MASK (0xff)
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#define ASPEED_CRYPTO_SRC_DMA_BUF_LEN 0xa000
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#define ASPEED_CRYPTO_DST_DMA_BUF_LEN 0xa000
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#define ASPEED_CRYPTO_GCM_TAG_OFFSET 0x9ff0
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#define ASPEED_HASH_SRC_DMA_BUF_LEN 0xa000
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#define ASPEED_HASH_QUEUE_LENGTH 50
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struct aspeed_hace_dev;
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typedef int (*aspeed_hace_fn_t)(struct aspeed_hace_dev *);
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struct aspeed_sg_list {
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__le32 len;
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__le32 phy_addr;
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};
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struct aspeed_engine_hash {
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struct tasklet_struct done_task;
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unsigned long flags;
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struct ahash_request *req;
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/* input buffer */
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void *ahash_src_addr;
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dma_addr_t ahash_src_dma_addr;
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dma_addr_t src_dma;
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dma_addr_t digest_dma;
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size_t src_length;
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/* callback func */
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aspeed_hace_fn_t resume;
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aspeed_hace_fn_t dma_prepare;
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};
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struct aspeed_sha_hmac_ctx {
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struct crypto_shash *shash;
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u8 ipad[SHA512_BLOCK_SIZE];
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u8 opad[SHA512_BLOCK_SIZE];
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};
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struct aspeed_sham_ctx {
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struct crypto_engine_ctx enginectx;
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struct aspeed_hace_dev *hace_dev;
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unsigned long flags; /* hmac flag */
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struct aspeed_sha_hmac_ctx base[0];
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};
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struct aspeed_sham_reqctx {
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unsigned long flags; /* final update flag should no use*/
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unsigned long op; /* final or update */
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u32 cmd; /* trigger cmd */
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/* walk state */
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struct scatterlist *src_sg;
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int src_nents;
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unsigned int offset; /* offset in current sg */
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unsigned int total; /* per update length */
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size_t digsize;
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size_t block_size;
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size_t ivsize;
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const __be32 *sha_iv;
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/* remain data buffer */
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u8 buffer[SHA512_BLOCK_SIZE * 2];
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dma_addr_t buffer_dma_addr;
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size_t bufcnt; /* buffer counter */
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/* output buffer */
|
||||
u8 digest[SHA512_DIGEST_SIZE] __aligned(64);
|
||||
dma_addr_t digest_dma_addr;
|
||||
u64 digcnt[2];
|
||||
};
|
||||
|
||||
struct aspeed_hace_dev {
|
||||
void __iomem *regs;
|
||||
struct device *dev;
|
||||
int irq;
|
||||
struct clk *clk;
|
||||
unsigned long version;
|
||||
|
||||
struct crypto_engine *crypt_engine_hash;
|
||||
|
||||
struct aspeed_engine_hash hash_engine;
|
||||
};
|
||||
|
||||
struct aspeed_hace_alg {
|
||||
struct aspeed_hace_dev *hace_dev;
|
||||
|
||||
const char *alg_base;
|
||||
|
||||
union {
|
||||
struct skcipher_alg skcipher;
|
||||
struct ahash_alg ahash;
|
||||
} alg;
|
||||
};
|
||||
|
||||
enum aspeed_version {
|
||||
AST2500_VERSION = 5,
|
||||
AST2600_VERSION
|
||||
};
|
||||
|
||||
#define ast_hace_write(hace, val, offset) \
|
||||
writel((val), (hace)->regs + (offset))
|
||||
#define ast_hace_read(hace, offset) \
|
||||
readl((hace)->regs + (offset))
|
||||
|
||||
void aspeed_register_hace_hash_algs(struct aspeed_hace_dev *hace_dev);
|
||||
void aspeed_unregister_hace_hash_algs(struct aspeed_hace_dev *hace_dev);
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user