drm/amd/display: Fix 300Hz Freesync bug
Needed to reprogram vblank_start in dml properly in order to get the correct dlg params to program VTG. Signed-off-by: Alvin Lee <alvin.lee2@amd.com> Reviewed-by: Martin Leung <Martin.Leung@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -287,7 +287,6 @@ bool dc_stream_adjust_vmin_vmax(struct dc *dc,
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struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
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if (pipe->stream == stream && pipe->stream_res.tg) {
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pipe->stream->adjust = *adjust;
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dc->hwss.set_drr(&pipe,
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1,
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adjust->v_total_min,
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@ -1883,12 +1883,14 @@ int dcn20_populate_dml_pipes_from_context(
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for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
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struct dc_crtc_timing *timing = &res_ctx->pipe_ctx[i].stream->timing;
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unsigned int v_total;
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unsigned int front_porch;
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int output_bpc;
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if (!res_ctx->pipe_ctx[i].stream)
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continue;
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v_total = timing->v_total;
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front_porch = timing->v_front_porch;
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/* todo:
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pipes[pipe_cnt].pipe.src.dynamic_metadata_enable = 0;
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pipes[pipe_cnt].pipe.src.dcc = 0;
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@ -1915,7 +1917,7 @@ int dcn20_populate_dml_pipes_from_context(
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- timing->h_addressable
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- timing->h_border_left
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- timing->h_border_right;
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pipes[pipe_cnt].pipe.dest.vblank_start = v_total - timing->v_front_porch;
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pipes[pipe_cnt].pipe.dest.vblank_start = v_total - front_porch;
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pipes[pipe_cnt].pipe.dest.vblank_end = pipes[pipe_cnt].pipe.dest.vblank_start
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- timing->v_addressable
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- timing->v_border_top
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@ -812,11 +812,12 @@ void mod_freesync_build_vrr_params(struct mod_freesync *mod_freesync,
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2 * in_out_vrr->min_refresh_in_uhz)
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in_out_vrr->btr.btr_enabled = false;
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in_out_vrr->fixed.fixed_active = false;
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in_out_vrr->btr.btr_active = false;
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in_out_vrr->btr.inserted_duration_in_us = 0;
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in_out_vrr->btr.frames_to_insert = 0;
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in_out_vrr->btr.frame_counter = 0;
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in_out_vrr->fixed.fixed_active = false;
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in_out_vrr->fixed.target_refresh_in_uhz = 0;
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in_out_vrr->btr.mid_point_in_us =
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(in_out_vrr->min_duration_in_us +
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