leandrof/linux
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

crypto: hisilicon - add new error type for SEC

Browse Source 
Kunpeng930 SEC adds several new hardware error types. This patch enables
the new error types and configures the error types as NFE.

Signed-off-by: Weili Qian <qianweili@huawei.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This commit is contained in:
Weili Qian 2021-04-12 20:31:34 +08:00 committed by Herbert Xu
parent b7220a7439
commit 10594d1e5f
1 changed files with 23 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

26
drivers/crypto/hisilicon/sec2/sec_main.c
View File

@ -42,8 +42,8 @@
#define SEC_ECC_NUM 16 #define SEC_ECC_NUM 16
#define SEC_ECC_MASH 0xFF #define SEC_ECC_MASH 0xFF
#define SEC_CORE_INT_DISABLE 0x0 #define SEC_CORE_INT_DISABLE 0x0
#define SEC_CORE_INT_ENABLE 0x1ff #define SEC_CORE_INT_ENABLE 0x7c1ff
#define SEC_CORE_INT_CLEAR 0x1ff #define SEC_CORE_INT_CLEAR 0x7c1ff
#define SEC_SAA_ENABLE 0x17f #define SEC_SAA_ENABLE 0x17f
#define SEC_RAS_CE_REG 0x301050 #define SEC_RAS_CE_REG 0x301050
@ -51,7 +51,7 @@
#define SEC_RAS_NFE_REG 0x301058 #define SEC_RAS_NFE_REG 0x301058
#define SEC_RAS_CE_ENB_MSK 0x88 #define SEC_RAS_CE_ENB_MSK 0x88
#define SEC_RAS_FE_ENB_MSK 0x0 #define SEC_RAS_FE_ENB_MSK 0x0
#define SEC_RAS_NFE_ENB_MSK 0x177 #define SEC_RAS_NFE_ENB_MSK 0x7c177
#define SEC_RAS_DISABLE 0x0 #define SEC_RAS_DISABLE 0x0
#define SEC_MEM_START_INIT_REG 0x301100 #define SEC_MEM_START_INIT_REG 0x301100
#define SEC_MEM_INIT_DONE_REG 0x301104 #define SEC_MEM_INIT_DONE_REG 0x301104
@ -147,6 +147,26 @@ static const struct sec_hw_error sec_hw_errors[] = {
.int_msk = BIT(8), .int_msk = BIT(8),
.msg = "sec_chain_buff_err_rint" .msg = "sec_chain_buff_err_rint"
}, },
{
.int_msk = BIT(14),
.msg = "sec_no_secure_access"
},
{
.int_msk = BIT(15),
.msg = "sec_wrapping_key_auth_err"
},
{
.int_msk = BIT(16),
.msg = "sec_km_key_crc_fail"
},
{
.int_msk = BIT(17),
.msg = "sec_axi_poison_err"
},
{
.int_msk = BIT(18),
.msg = "sec_sva_err"
},
{} {}
}; };