mtd: nand: Pass the CS line to ->setup_data_interface()
Some NAND controllers can assign different NAND timings to different CS lines. Pass the CS line information to ->setup_data_interface() so that the NAND controller driver knows which CS line is concerned by the setup_data_interface() request. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
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ebb528d978
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104e442a67
@ -388,9 +388,8 @@ static int fsmc_calc_timings(struct fsmc_nand_data *host,
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return 0;
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}
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static int fsmc_setup_data_interface(struct mtd_info *mtd,
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const struct nand_data_interface *conf,
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bool check_only)
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static int fsmc_setup_data_interface(struct mtd_info *mtd, int csline,
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const struct nand_data_interface *conf)
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{
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struct nand_chip *nand = mtd_to_nand(mtd);
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struct fsmc_nand_data *host = nand_get_controller_data(nand);
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@ -406,7 +405,7 @@ static int fsmc_setup_data_interface(struct mtd_info *mtd,
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if (ret)
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return ret;
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if (check_only)
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if (csline == NAND_DATA_IFACE_CHECK_ONLY)
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return 0;
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fsmc_nand_setup(host, &tims);
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@ -152,9 +152,8 @@ struct mxc_nand_devtype_data {
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void (*select_chip)(struct mtd_info *mtd, int chip);
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int (*correct_data)(struct mtd_info *mtd, u_char *dat,
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u_char *read_ecc, u_char *calc_ecc);
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int (*setup_data_interface)(struct mtd_info *mtd,
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const struct nand_data_interface *conf,
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bool check_only);
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int (*setup_data_interface)(struct mtd_info *mtd, int csline,
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const struct nand_data_interface *conf);
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/*
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* On i.MX21 the CONFIG2:INT bit cannot be read if interrupts are masked
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@ -1015,9 +1014,8 @@ static void preset_v1(struct mtd_info *mtd)
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writew(0x4, NFC_V1_V2_WRPROT);
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}
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static int mxc_nand_v2_setup_data_interface(struct mtd_info *mtd,
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const struct nand_data_interface *conf,
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bool check_only)
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static int mxc_nand_v2_setup_data_interface(struct mtd_info *mtd, int csline,
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const struct nand_data_interface *conf)
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{
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struct nand_chip *nand_chip = mtd_to_nand(mtd);
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struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
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@ -1075,7 +1073,7 @@ static int mxc_nand_v2_setup_data_interface(struct mtd_info *mtd,
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return -EINVAL;
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}
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if (check_only)
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if (csline == NAND_DATA_IFACE_CHECK_ONLY)
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return 0;
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ret = clk_set_rate(host->clk, rate);
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@ -1042,12 +1042,13 @@ static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
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/**
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* nand_reset_data_interface - Reset data interface and timings
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* @chip: The NAND chip
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* @chipnr: Internal die id
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*
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* Reset the Data interface and timings to ONFI mode 0.
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*
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* Returns 0 for success or negative error code otherwise.
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*/
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static int nand_reset_data_interface(struct nand_chip *chip)
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static int nand_reset_data_interface(struct nand_chip *chip, int chipnr)
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{
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struct mtd_info *mtd = nand_to_mtd(chip);
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const struct nand_data_interface *conf;
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@ -1071,7 +1072,7 @@ static int nand_reset_data_interface(struct nand_chip *chip)
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*/
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conf = nand_get_default_data_interface();
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ret = chip->setup_data_interface(mtd, conf, false);
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ret = chip->setup_data_interface(mtd, chipnr, conf);
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if (ret)
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pr_err("Failed to configure data interface to SDR timing mode 0\n");
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@ -1081,6 +1082,7 @@ static int nand_reset_data_interface(struct nand_chip *chip)
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/**
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* nand_setup_data_interface - Setup the best data interface and timings
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* @chip: The NAND chip
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* @chipnr: Internal die id
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*
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* Find and configure the best data interface and NAND timings supported by
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* the chip and the driver.
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@ -1090,7 +1092,7 @@ static int nand_reset_data_interface(struct nand_chip *chip)
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*
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* Returns 0 for success or negative error code otherwise.
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*/
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static int nand_setup_data_interface(struct nand_chip *chip)
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static int nand_setup_data_interface(struct nand_chip *chip, int chipnr)
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{
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struct mtd_info *mtd = nand_to_mtd(chip);
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int ret;
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@ -1114,7 +1116,7 @@ static int nand_setup_data_interface(struct nand_chip *chip)
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goto err;
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}
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ret = chip->setup_data_interface(mtd, chip->data_interface, false);
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ret = chip->setup_data_interface(mtd, chipnr, chip->data_interface);
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err:
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return ret;
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}
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@ -1165,8 +1167,10 @@ static int nand_init_data_interface(struct nand_chip *chip)
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if (ret)
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continue;
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ret = chip->setup_data_interface(mtd, chip->data_interface,
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true);
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/* Pass -1 to only */
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ret = chip->setup_data_interface(mtd,
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NAND_DATA_IFACE_CHECK_ONLY,
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chip->data_interface);
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if (!ret) {
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chip->onfi_timing_mode_default = mode;
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break;
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@ -1193,7 +1197,7 @@ int nand_reset(struct nand_chip *chip, int chipnr)
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struct mtd_info *mtd = nand_to_mtd(chip);
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int ret;
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ret = nand_reset_data_interface(chip);
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ret = nand_reset_data_interface(chip, chipnr);
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if (ret)
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return ret;
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@ -1206,7 +1210,7 @@ int nand_reset(struct nand_chip *chip, int chipnr)
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chip->select_chip(mtd, -1);
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chip->select_chip(mtd, chipnr);
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ret = nand_setup_data_interface(chip);
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ret = nand_setup_data_interface(chip, chipnr);
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chip->select_chip(mtd, -1);
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if (ret)
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return ret;
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@ -4396,7 +4400,7 @@ int nand_scan_ident(struct mtd_info *mtd, int maxchips,
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* For the other dies, nand_reset() will automatically switch to the
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* best mode for us.
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*/
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ret = nand_setup_data_interface(chip);
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ret = nand_setup_data_interface(chip, 0);
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if (ret)
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return ret;
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@ -812,9 +812,8 @@ static int s3c2410_nand_add_partition(struct s3c2410_nand_info *info,
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return -ENODEV;
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}
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static int s3c2410_nand_setup_data_interface(struct mtd_info *mtd,
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const struct nand_data_interface *conf,
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bool check_only)
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static int s3c2410_nand_setup_data_interface(struct mtd_info *mtd, int csline,
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const struct nand_data_interface *conf)
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{
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struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
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struct s3c2410_platform_nand *pdata = info->platform;
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@ -1592,9 +1592,8 @@ static int _sunxi_nand_lookup_timing(const s32 *lut, int lut_size, u32 duration,
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#define sunxi_nand_lookup_timing(l, p, c) \
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_sunxi_nand_lookup_timing(l, ARRAY_SIZE(l), p, c)
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static int sunxi_nfc_setup_data_interface(struct mtd_info *mtd,
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const struct nand_data_interface *conf,
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bool check_only)
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static int sunxi_nfc_setup_data_interface(struct mtd_info *mtd, int csline,
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const struct nand_data_interface *conf)
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{
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struct nand_chip *nand = mtd_to_nand(mtd);
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struct sunxi_nand_chip *chip = to_sunxi_nand(nand);
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@ -1707,7 +1706,7 @@ static int sunxi_nfc_setup_data_interface(struct mtd_info *mtd,
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return tRHW;
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}
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if (check_only)
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if (csline == NAND_DATA_IFACE_CHECK_ONLY)
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return 0;
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/*
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@ -476,9 +476,8 @@ static u32 to_ticks(int kHz, int ps)
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return DIV_ROUND_UP_ULL((u64)kHz * ps, NSEC_PER_SEC);
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}
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static int tango_set_timings(struct mtd_info *mtd,
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const struct nand_data_interface *conf,
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bool check_only)
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static int tango_set_timings(struct mtd_info *mtd, int csline,
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const struct nand_data_interface *conf)
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{
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const struct nand_sdr_timings *sdr = nand_get_sdr_timings(conf);
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struct nand_chip *chip = mtd_to_nand(mtd);
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@ -490,7 +489,7 @@ static int tango_set_timings(struct mtd_info *mtd,
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if (IS_ERR(sdr))
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return PTR_ERR(sdr);
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if (check_only)
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if (csline == NAND_DATA_IFACE_CHECK_ONLY)
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return 0;
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Trdy = to_ticks(kHz, sdr->tCEA_max - sdr->tREA_max);
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@ -107,6 +107,8 @@ int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
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#define NAND_STATUS_READY 0x40
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#define NAND_STATUS_WP 0x80
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#define NAND_DATA_IFACE_CHECK_ONLY -1
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/*
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* Constants for ECC_MODES
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*/
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@ -818,7 +820,10 @@ struct nand_manufacturer_ops {
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* @read_retries: [INTERN] the number of read retry modes supported
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* @onfi_set_features: [REPLACEABLE] set the features for ONFI nand
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* @onfi_get_features: [REPLACEABLE] get the features for ONFI nand
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* @setup_data_interface: [OPTIONAL] setup the data interface and timing
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* @setup_data_interface: [OPTIONAL] setup the data interface and timing. If
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* chipnr is set to %NAND_DATA_IFACE_CHECK_ONLY this
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* means the configuration should not be applied but
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* only checked.
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* @bbt: [INTERN] bad block table pointer
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* @bbt_td: [REPLACEABLE] bad block table descriptor for flash
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* lookup.
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@ -862,9 +867,8 @@ struct nand_chip {
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int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip,
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int feature_addr, uint8_t *subfeature_para);
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int (*setup_read_retry)(struct mtd_info *mtd, int retry_mode);
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int (*setup_data_interface)(struct mtd_info *mtd,
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const struct nand_data_interface *conf,
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bool check_only);
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int (*setup_data_interface)(struct mtd_info *mtd, int chipnr,
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const struct nand_data_interface *conf);
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int chip_delay;
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