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arm64: dts: qcom: msm8998: Add I2C pinctrl and fix BLSP2_I2C naming

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The BLSP2-connected interfaces started from 0 which is.. misleading
to say the least.. the clock names corresponding to these started
from 1, so let's align to that so as to reduce confusion.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Link: https://lore.kernel.org/r/20210109163001.146867-4-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
This commit is contained in:
Konrad Dybcio 2021-01-09 17:29:57 +01:00 committed by Bjorn Andersson
parent 6845359eea
commit 0fee55fc0d
1 changed files with 210 additions and 6 deletions
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216
arch/arm64/boot/dts/qcom/msm8998.dtsi
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@ -1177,6 +1177,174 @@
bias-disable; bias-disable;
}; };
}; };
blsp1_i2c1_default: blsp1-i2c1-default {
pins = "gpio2", "gpio3";
function = "blsp_i2c1";
drive-strength = <2>;
bias-disable;
};
blsp1_i2c1_sleep: blsp1-i2c1-sleep {
pins = "gpio2", "gpio3";
function = "blsp_i2c1";
drive-strength = <2>;
bias-pull-up;
};
blsp1_i2c2_default: blsp1-i2c2-default {
pins = "gpio32", "gpio33";
function = "blsp_i2c2";
drive-strength = <2>;
bias-disable;
};
blsp1_i2c2_sleep: blsp1-i2c2-sleep {
pins = "gpio32", "gpio33";
function = "blsp_i2c2";
drive-strength = <2>;
bias-pull-up;
};
blsp1_i2c3_default: blsp1-i2c3-default {
pins = "gpio47", "gpio48";
function = "blsp_i2c3";
drive-strength = <2>;
bias-disable;
};
blsp1_i2c3_sleep: blsp1-i2c3-sleep {
pins = "gpio47", "gpio48";
function = "blsp_i2c3";
drive-strength = <2>;
bias-pull-up;
};
blsp1_i2c4_default: blsp1-i2c4-default {
pins = "gpio10", "gpio11";
function = "blsp_i2c4";
drive-strength = <2>;
bias-disable;
};
blsp1_i2c4_sleep: blsp1-i2c4-sleep {
pins = "gpio10", "gpio11";
function = "blsp_i2c4";
drive-strength = <2>;
bias-pull-up;
};
blsp1_i2c5_default: blsp1-i2c5-default {
pins = "gpio87", "gpio88";
function = "blsp_i2c5";
drive-strength = <2>;
bias-disable;
};
blsp1_i2c5_sleep: blsp1-i2c5-sleep {
pins = "gpio87", "gpio88";
function = "blsp_i2c5";
drive-strength = <2>;
bias-pull-up;
};
blsp1_i2c6_default: blsp1-i2c6-default {
pins = "gpio43", "gpio44";
function = "blsp_i2c6";
drive-strength = <2>;
bias-disable;
};
blsp1_i2c6_sleep: blsp1-i2c6-sleep {
pins = "gpio43", "gpio44";
function = "blsp_i2c6";
drive-strength = <2>;
bias-pull-up;
};
/* 6 interfaces per QUP, BLSP2 indexes are numbered (n)+6 */
blsp2_i2c1_default: blsp2-i2c1-default {
pins = "gpio55", "gpio56";
function = "blsp_i2c7";
drive-strength = <2>;
bias-disable;
};
blsp2_i2c1_sleep: blsp2-i2c1-sleep {
pins = "gpio55", "gpio56";
function = "blsp_i2c7";
drive-strength = <2>;
bias-pull-up;
};
blsp2_i2c2_default: blsp2-i2c2-default {
pins = "gpio6", "gpio7";
function = "blsp_i2c8";
drive-strength = <2>;
bias-disable;
};
blsp2_i2c2_sleep: blsp2-i2c2-sleep {
pins = "gpio6", "gpio7";
function = "blsp_i2c8";
drive-strength = <2>;
bias-pull-up;
};
blsp2_i2c3_default: blsp2-i2c3-default {
pins = "gpio51", "gpio52";
function = "blsp_i2c9";
drive-strength = <2>;
bias-disable;
};
blsp2_i2c3_sleep: blsp2-i2c3-sleep {
pins = "gpio51", "gpio52";
function = "blsp_i2c9";
drive-strength = <2>;
bias-pull-up;
};
blsp2_i2c4_default: blsp2-i2c4-default {
pins = "gpio67", "gpio68";
function = "blsp_i2c10";
drive-strength = <2>;
bias-disable;
};
blsp2_i2c4_sleep: blsp2-i2c4-sleep {
pins = "gpio67", "gpio68";
function = "blsp_i2c10";
drive-strength = <2>;
bias-pull-up;
};
blsp2_i2c5_default: blsp2-i2c5-default {
pins = "gpio60", "gpio61";
function = "blsp_i2c11";
drive-strength = <2>;
bias-disable;
};
blsp2_i2c5_sleep: blsp2-i2c5-sleep {
pins = "gpio60", "gpio61";
function = "blsp_i2c11";
drive-strength = <2>;
bias-pull-up;
};
blsp2_i2c6_default: blsp2-i2c6-default {
pins = "gpio83", "gpio84";
function = "blsp_i2c12";
drive-strength = <2>;
bias-disable;
};
blsp2_i2c6_sleep: blsp2-i2c6-sleep {
pins = "gpio83", "gpio84";
function = "blsp_i2c12";
drive-strength = <2>;
bias-pull-up;
};
}; };
remoteproc_mss: remoteproc@4080000 { remoteproc_mss: remoteproc@4080000 {
@ -1895,6 +2063,9 @@
clock-names = "core", "iface"; clock-names = "core", "iface";
dmas = <&blsp1_dma 6>, <&blsp1_dma 7>; dmas = <&blsp1_dma 6>, <&blsp1_dma 7>;
dma-names = "tx", "rx"; dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp1_i2c1_default>;
pinctrl-1 = <&blsp1_i2c1_sleep>;
clock-frequency = <400000>; clock-frequency = <400000>;
status = "disabled"; status = "disabled";
@ -1912,6 +2083,9 @@
clock-names = "core", "iface"; clock-names = "core", "iface";
dmas = <&blsp1_dma 8>, <&blsp1_dma 9>; dmas = <&blsp1_dma 8>, <&blsp1_dma 9>;
dma-names = "tx", "rx"; dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp1_i2c2_default>;
pinctrl-1 = <&blsp1_i2c2_sleep>;
clock-frequency = <400000>; clock-frequency = <400000>;
status = "disabled"; status = "disabled";
@ -1929,6 +2103,9 @@
clock-names = "core", "iface"; clock-names = "core", "iface";
dmas = <&blsp1_dma 10>, <&blsp1_dma 11>; dmas = <&blsp1_dma 10>, <&blsp1_dma 11>;
dma-names = "tx", "rx"; dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp1_i2c3_default>;
pinctrl-1 = <&blsp1_i2c3_sleep>;
clock-frequency = <400000>; clock-frequency = <400000>;
status = "disabled"; status = "disabled";
@ -1946,6 +2123,9 @@
clock-names = "core", "iface"; clock-names = "core", "iface";
dmas = <&blsp1_dma 12>, <&blsp1_dma 13>; dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
dma-names = "tx", "rx"; dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp1_i2c4_default>;
pinctrl-1 = <&blsp1_i2c4_sleep>;
clock-frequency = <400000>; clock-frequency = <400000>;
status = "disabled"; status = "disabled";
@ -1963,6 +2143,9 @@
clock-names = "core", "iface"; clock-names = "core", "iface";
dmas = <&blsp1_dma 14>, <&blsp1_dma 15>; dmas = <&blsp1_dma 14>, <&blsp1_dma 15>;
dma-names = "tx", "rx"; dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp1_i2c5_default>;
pinctrl-1 = <&blsp1_i2c5_sleep>;
clock-frequency = <400000>; clock-frequency = <400000>;
status = "disabled"; status = "disabled";
@ -1980,6 +2163,9 @@
clock-names = "core", "iface"; clock-names = "core", "iface";
dmas = <&blsp1_dma 16>, <&blsp1_dma 17>; dmas = <&blsp1_dma 16>, <&blsp1_dma 17>;
dma-names = "tx", "rx"; dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp1_i2c6_default>;
pinctrl-1 = <&blsp1_i2c6_sleep>;
clock-frequency = <400000>; clock-frequency = <400000>;
status = "disabled"; status = "disabled";
@ -2010,7 +2196,7 @@
status = "disabled"; status = "disabled";
}; };
blsp2_i2c0: i2c@c1b5000 { blsp2_i2c1: i2c@c1b5000 {
compatible = "qcom,i2c-qup-v2.2.1"; compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x0c1b5000 0x600>; reg = <0x0c1b5000 0x600>;
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
@ -2020,6 +2206,9 @@
clock-names = "core", "iface"; clock-names = "core", "iface";
dmas = <&blsp2_dma 6>, <&blsp2_dma 7>; dmas = <&blsp2_dma 6>, <&blsp2_dma 7>;
dma-names = "tx", "rx"; dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp2_i2c1_default>;
pinctrl-1 = <&blsp2_i2c1_sleep>;
clock-frequency = <400000>; clock-frequency = <400000>;
status = "disabled"; status = "disabled";
@ -2027,7 +2216,7 @@
#size-cells = <0>; #size-cells = <0>;
}; };
blsp2_i2c1: i2c@c1b6000 { blsp2_i2c2: i2c@c1b6000 {
compatible = "qcom,i2c-qup-v2.2.1"; compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x0c1b6000 0x600>; reg = <0x0c1b6000 0x600>;
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
@ -2037,6 +2226,9 @@
clock-names = "core", "iface"; clock-names = "core", "iface";
dmas = <&blsp2_dma 8>, <&blsp2_dma 9>; dmas = <&blsp2_dma 8>, <&blsp2_dma 9>;
dma-names = "tx", "rx"; dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp2_i2c2_default>;
pinctrl-1 = <&blsp2_i2c2_sleep>;
clock-frequency = <400000>; clock-frequency = <400000>;
status = "disabled"; status = "disabled";
@ -2044,7 +2236,7 @@
#size-cells = <0>; #size-cells = <0>;
}; };
blsp2_i2c2: i2c@c1b7000 { blsp2_i2c3: i2c@c1b7000 {
compatible = "qcom,i2c-qup-v2.2.1"; compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x0c1b7000 0x600>; reg = <0x0c1b7000 0x600>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
@ -2054,6 +2246,9 @@
clock-names = "core", "iface"; clock-names = "core", "iface";
dmas = <&blsp2_dma 10>, <&blsp2_dma 11>; dmas = <&blsp2_dma 10>, <&blsp2_dma 11>;
dma-names = "tx", "rx"; dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp2_i2c3_default>;
pinctrl-1 = <&blsp2_i2c3_sleep>;
clock-frequency = <400000>; clock-frequency = <400000>;
status = "disabled"; status = "disabled";
@ -2061,7 +2256,7 @@
#size-cells = <0>; #size-cells = <0>;
}; };
blsp2_i2c3: i2c@c1b8000 { blsp2_i2c4: i2c@c1b8000 {
compatible = "qcom,i2c-qup-v2.2.1"; compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x0c1b8000 0x600>; reg = <0x0c1b8000 0x600>;
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
@ -2071,6 +2266,9 @@
clock-names = "core", "iface"; clock-names = "core", "iface";
dmas = <&blsp2_dma 12>, <&blsp2_dma 13>; dmas = <&blsp2_dma 12>, <&blsp2_dma 13>;
dma-names = "tx", "rx"; dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp2_i2c4_default>;
pinctrl-1 = <&blsp2_i2c4_sleep>;
clock-frequency = <400000>; clock-frequency = <400000>;
status = "disabled"; status = "disabled";
@ -2078,7 +2276,7 @@
#size-cells = <0>; #size-cells = <0>;
}; };
blsp2_i2c4: i2c@c1b9000 { blsp2_i2c5: i2c@c1b9000 {
compatible = "qcom,i2c-qup-v2.2.1"; compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x0c1b9000 0x600>; reg = <0x0c1b9000 0x600>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
@ -2088,6 +2286,9 @@
clock-names = "core", "iface"; clock-names = "core", "iface";
dmas = <&blsp2_dma 14>, <&blsp2_dma 15>; dmas = <&blsp2_dma 14>, <&blsp2_dma 15>;
dma-names = "tx", "rx"; dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp2_i2c5_default>;
pinctrl-1 = <&blsp2_i2c5_sleep>;
clock-frequency = <400000>; clock-frequency = <400000>;
status = "disabled"; status = "disabled";
@ -2095,7 +2296,7 @@
#size-cells = <0>; #size-cells = <0>;
}; };
blsp2_i2c5: i2c@c1ba000 { blsp2_i2c6: i2c@c1ba000 {
compatible = "qcom,i2c-qup-v2.2.1"; compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x0c1ba000 0x600>; reg = <0x0c1ba000 0x600>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
@ -2105,6 +2306,9 @@
clock-names = "core", "iface"; clock-names = "core", "iface";
dmas = <&blsp2_dma 16>, <&blsp2_dma 17>; dmas = <&blsp2_dma 16>, <&blsp2_dma 17>;
dma-names = "tx", "rx"; dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp2_i2c6_default>;
pinctrl-1 = <&blsp2_i2c6_sleep>;
clock-frequency = <400000>; clock-frequency = <400000>;
status = "disabled"; status = "disabled";