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arm64: dts: renesas: r8a77951: Add PCIe EP nodes

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Add PCIe EP nodes for R8A77951 SoC dtsi.

Signed-off-by: Yuya Hamamachi <yuya.hamamachi.sx@renesas.com>
Link: https://lore.kernel.org/r/20201125073303.19057-3-yuya.hamamachi.sx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
This commit is contained in:
Yuya Hamamachi 2020-11-25 16:33:03 +09:00 committed by Geert Uytterhoeven
parent 43bba65761
commit 0f80b9b812
1 changed files with 38 additions and 0 deletions
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38
arch/arm64/boot/dts/renesas/r8a77951.dtsi
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@ -2727,6 +2727,44 @@
status = "disabled";
};
pciec0_ep: pcie-ep@fe000000 {
compatible = "renesas,r8a7795-pcie-ep",
"renesas,rcar-gen3-pcie-ep";
reg = <0x0 0xfe000000 0 0x80000>,
<0x0 0xfe100000 0 0x100000>,
<0x0 0xfe200000 0 0x200000>,
<0x0 0x30000000 0 0x8000000>,
<0x0 0x38000000 0 0x8000000>;
reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 319>;
clock-names = "pcie";
resets = <&cpg 319>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
status = "disabled";
};
pciec1_ep: pcie-ep@ee800000 {
compatible = "renesas,r8a7795-pcie-ep",
"renesas,rcar-gen3-pcie-ep";
reg = <0x0 0xee800000 0 0x80000>,
<0x0 0xee900000 0 0x100000>,
<0x0 0xeea00000 0 0x200000>,
<0x0 0xc0000000 0 0x8000000>,
<0x0 0xc8000000 0 0x8000000>;
reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 318>;
clock-names = "pcie";
resets = <&cpg 318>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
status = "disabled";
};
imr-lx4@fe860000 {
compatible = "renesas,r8a7795-imr-lx4",
"renesas,imr-lx4";