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Allwinner DT changes for 5.1

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As usual, this is a random assortment of changes:
 
   - ARM PMU is enabled on the A10
   - The first usage of the PIO pinbank regulator supplies added,
     for the Bananapi
   - Broadcom-based Bluetooth enabled on the Bananapi M2 Magic and M2
     Ultra, using the serdev bindings
   - Video codec added for the A10
   - Display pipeline for the A23 added and enabled for the generic Q8
     tablets
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Merge tag 'sunxi-dt-for-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/dt

Allwinner DT changes for 5.1

As usual, this is a random assortment of changes:

  - ARM PMU is enabled on the A10
  - The first usage of the PIO pinbank regulator supplies added,
    for the Bananapi
  - Broadcom-based Bluetooth enabled on the Bananapi M2 Magic and M2
    Ultra, using the serdev bindings
  - Video codec added for the A10
  - Display pipeline for the A23 added and enabled for the generic Q8
    tablets

* tag 'sunxi-dt-for-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  ARM: dts: sun8i-a23-q8: Set compatible string for LCD panel
  ARM: dts: sun8i-q8-common: Enable display pipeline with RGB LCD panel
  ARM: dts: sun8i-a23: Add compatible strings to display pipeline device nodes
  ARM: dts: sun8i-a33: Move display pipeline nodes to a23/a33 common dtsi
  ARM: dts: sun8i-a23-a33: Move NAND controller device node to sort by address
  ARM: dts: sun4i-a10: Add Video Engine and reserved memory nodes
  ARM: dts: sun4i: Add support for the C1 SRAM region with the SRAM controller
  ARM: dts: sunxi: bananapi-m2-plus: Add Bluetooth device node
  ARM: dts: sun8i: r40: bananapi-m2-ultra: Add Bluetooth device node
  ARM: dts: sun8i: r40: bananapi-m2-ultra: Fix WiFi regulator definitions
  ARM: dts: sun8i: r40: Add pinmux setting for CLK_OUT_A
  ARM: dts: sun8i: r40: Add pinmux settings for UART3 on PG pingroup
  ARM: dts: sun7i: bananapi: Add GPIO banks regulators
  ARM: dts: sun4i-a10: Add PMU node

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2019-01-30 17:55:57 +01:00
commit 0f7be8f5bd
10 changed files with 378 additions and 171 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

44
arch/arm/boot/dts/sun4i-a10.dtsi
View File

@ -184,6 +184,26 @@
status = "disabled";
};
pmu {
compatible = "arm,cortex-a8-pmu";
interrupts = <3>;
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
/* Address must be kept in the lower 256 MiBs of DRAM for VE. */
default-pool {
compatible = "shared-dma-pool";
size = <0x6000000>;
alloc-ranges = <0x4a000000 0x6000000>;
reusable;
linux,cma-default;
};
};
soc {
compatible = "simple-bus";
#address-cells = <1>;
@ -224,6 +244,19 @@
status = "disabled";
};
};
sram_c: sram@1d00000 {
compatible = "mmio-sram";
reg = <0x01d00000 0xd0000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x01d00000 0xd0000>;
ve_sram: sram-section@0 {
compatible = "allwinner,sun4i-a10-sram-c1";
reg = <0x000000 0x80000>;
};
};
};
dma: dma-controller@1c02000 {
@ -394,6 +427,17 @@
};
};
video-codec@1c0e000 {
compatible = "allwinner,sun4i-a10-video-engine";
reg = <0x01c0e000 0x1000>;
clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>,
<&ccu CLK_DRAM_VE>;
clock-names = "ahb", "mod", "ram";
resets = <&ccu RST_VE>;
interrupts = <53>;
allwinner,sram = <&ve_sram 1>;
};
mmc0: mmc@1c0f000 {
compatible = "allwinner,sun4i-a10-mmc";
reg = <0x01c0f000 0x1000>;

5
arch/arm/boot/dts/sun7i-a20-bananapi.dts
View File

@ -191,6 +191,11 @@
};
&pio {
vcc-pa-supply = <&reg_vcc3v3>;
vcc-pc-supply = <&reg_vcc3v3>;
vcc-pe-supply = <&reg_vcc3v3>;
vcc-pf-supply = <&reg_vcc3v3>;
vcc-pg-supply = <&reg_vcc3v3>;
gpio-line-names =
/* PA */
"ERXD3", "ERXD2", "ERXD1", "ERXD0", "ETXD3",

175
arch/arm/boot/dts/sun8i-a23-a33.dtsi
View File

@ -68,6 +68,12 @@
};
};
de: display-engine {
/* compatible gets set in SoC specific dtsi file */
allwinner,pipelines = <&fe0>;
status = "disabled";
};
timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
@ -155,6 +161,55 @@
#dma-cells = <1>;
};
nfc: nand@1c03000 {
compatible = "allwinner,sun4i-a10-nand";
reg = <0x01c03000 0x1000>;
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_NAND>, <&ccu CLK_NAND>;
clock-names = "ahb", "mod";
resets = <&ccu RST_BUS_NAND>;
reset-names = "ahb";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
tcon0: lcd-controller@1c0c000 {
/* compatible gets set in SoC specific dtsi file */
reg = <0x01c0c000 0x1000>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_LCD>,
<&ccu CLK_LCD_CH0>;
clock-names = "ahb",
"tcon-ch0";
clock-output-names = "tcon-pixel-clock";
resets = <&ccu RST_BUS_LCD>;
reset-names = "lcd";
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
tcon0_in: port@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
tcon0_in_drc0: endpoint@0 {
reg = <0>;
remote-endpoint = <&drc0_out_tcon0>;
};
};
tcon0_out: port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
};
};
};
mmc0: mmc@1c0f000 {
compatible = "allwinner,sun7i-a20-mmc";
reg = <0x01c0f000 0x1000>;
@ -214,21 +269,6 @@
#size-cells = <0>;
};
nfc: nand@1c03000 {
compatible = "allwinner,sun4i-a10-nand";
reg = <0x01c03000 0x1000>;
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_NAND>, <&ccu CLK_NAND>;
clock-names = "ahb", "mod";
resets = <&ccu RST_BUS_NAND>;
reset-names = "ahb";
pinctrl-names = "default";
pinctrl-0 = <&nand_pins &nand_pins_cs0 &nand_pins_rb0>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
usb_otg: usb@1c19000 {
/* compatible gets set in SoC specific dtsi file */
reg = <0x01c19000 0x0400>;
@ -572,6 +612,111 @@
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
fe0: display-frontend@1e00000 {
/* compatible gets set in SoC specific dtsi file */
reg = <0x01e00000 0x20000>;
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_DE_FE>, <&ccu CLK_DE_FE>,
<&ccu CLK_DRAM_DE_FE>;
clock-names = "ahb", "mod",
"ram";
resets = <&ccu RST_BUS_DE_FE>;
ports {
#address-cells = <1>;
#size-cells = <0>;
fe0_out: port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
fe0_out_be0: endpoint@0 {
reg = <0>;
remote-endpoint = <&be0_in_fe0>;
};
};
};
};
be0: display-backend@1e60000 {
/* compatible gets set in SoC specific dtsi file */
reg = <0x01e60000 0x10000>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>,
<&ccu CLK_DRAM_DE_BE>;
clock-names = "ahb", "mod",
"ram";
resets = <&ccu RST_BUS_DE_BE>;
ports {
#address-cells = <1>;
#size-cells = <0>;
be0_in: port@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
be0_in_fe0: endpoint@0 {
reg = <0>;
remote-endpoint = <&fe0_out_be0>;
};
};
be0_out: port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
be0_out_drc0: endpoint@0 {
reg = <0>;
remote-endpoint = <&drc0_in_be0>;
};
};
};
};
drc0: drc@1e70000 {
/* compatible gets set in SoC specific dtsi file */
reg = <0x01e70000 0x10000>;
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_DRC>, <&ccu CLK_DRC>,
<&ccu CLK_DRAM_DRC>;
clock-names = "ahb", "mod", "ram";
resets = <&ccu RST_BUS_DRC>;
assigned-clocks = <&ccu CLK_DRC>;
assigned-clock-rates = <300000000>;
ports {
#address-cells = <1>;
#size-cells = <0>;
drc0_in: port@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
drc0_in_be0: endpoint@0 {
reg = <0>;
remote-endpoint = <&be0_out_drc0>;
};
};
drc0_out: port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
drc0_out_tcon0: endpoint@0 {
reg = <0>;
remote-endpoint = <&tcon0_in_drc0>;
};
};
};
};
rtc: rtc@1f00000 {
compatible = "allwinner,sun8i-a23-rtc";
reg = <0x01f00000 0x400>;

4
arch/arm/boot/dts/sun8i-a23-q8-tablet.dts
View File

@ -61,3 +61,7 @@
"Headset Mic", "HBIAS";
status = "okay";
};
&panel {
compatible = "bananapi,s070wv20-ct16", "simple-panel";
};

20
arch/arm/boot/dts/sun8i-a23.dtsi
View File

@ -62,10 +62,26 @@
};
};
&be0 {
compatible = "allwinner,sun8i-a23-display-backend";
};
&ccu {
compatible = "allwinner,sun8i-a23-ccu";
};
&de {
compatible = "allwinner,sun8i-a23-display-engine";
};
&drc0 {
compatible = "allwinner,sun8i-a23-drc";
};
&fe0 {
compatible = "allwinner,sun8i-a23-display-frontend";
};
&pio {
compatible = "allwinner,sun8i-a23-pinctrl";
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
@ -73,6 +89,10 @@
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
};
&tcon0 {
compatible = "allwinner,sun8i-a23-tcon";
};
&usb_otg {
compatible = "allwinner,sun6i-a31-musb";
};

194
arch/arm/boot/dts/sun8i-a33.dtsi
View File

@ -159,12 +159,6 @@
};
};
de: display-engine {
compatible = "allwinner,sun8i-a33-display-engine";
allwinner,pipelines = <&fe0>;
status = "disabled";
};
iio-hwmon {
compatible = "iio-hwmon";
io-channels = <&ths>;
@ -209,47 +203,6 @@
};
soc {
tcon0: lcd-controller@1c0c000 {
compatible = "allwinner,sun8i-a33-tcon";
reg = <0x01c0c000 0x1000>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_LCD>,
<&ccu CLK_LCD_CH0>;
clock-names = "ahb",
"tcon-ch0";
clock-output-names = "tcon-pixel-clock";
resets = <&ccu RST_BUS_LCD>;
reset-names = "lcd";
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
tcon0_in: port@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
tcon0_in_drc0: endpoint@0 {
reg = <0>;
remote-endpoint = <&drc0_out_tcon0>;
};
};
tcon0_out: port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
tcon0_out_dsi: endpoint@1 {
reg = <1>;
remote-endpoint = <&dsi_in_tcon0>;
};
};
};
};
video-codec@1c0e000 {
compatible = "allwinner,sun8i-a33-video-engine";
reg = <0x01c0e000 0x1000>;
@ -339,115 +292,6 @@
status = "disabled";
#phy-cells = <0>;
};
fe0: display-frontend@1e00000 {
compatible = "allwinner,sun8i-a33-display-frontend";
reg = <0x01e00000 0x20000>;
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_DE_FE>, <&ccu CLK_DE_FE>,
<&ccu CLK_DRAM_DE_FE>;
clock-names = "ahb", "mod",
"ram";
resets = <&ccu RST_BUS_DE_FE>;
ports {
#address-cells = <1>;
#size-cells = <0>;
fe0_out: port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
fe0_out_be0: endpoint@0 {
reg = <0>;
remote-endpoint = <&be0_in_fe0>;
};
};
};
};
be0: display-backend@1e60000 {
compatible = "allwinner,sun8i-a33-display-backend";
reg = <0x01e60000 0x10000>, <0x01e80000 0x1000>;
reg-names = "be", "sat";
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>,
<&ccu CLK_DRAM_DE_BE>, <&ccu CLK_BUS_SAT>;
clock-names = "ahb", "mod",
"ram", "sat";
resets = <&ccu RST_BUS_DE_BE>, <&ccu RST_BUS_SAT>;
reset-names = "be", "sat";
assigned-clocks = <&ccu CLK_DE_BE>;
assigned-clock-rates = <300000000>;
ports {
#address-cells = <1>;
#size-cells = <0>;
be0_in: port@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
be0_in_fe0: endpoint@0 {
reg = <0>;
remote-endpoint = <&fe0_out_be0>;
};
};
be0_out: port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
be0_out_drc0: endpoint@0 {
reg = <0>;
remote-endpoint = <&drc0_in_be0>;
};
};
};
};
drc0: drc@1e70000 {
compatible = "allwinner,sun8i-a33-drc";
reg = <0x01e70000 0x10000>;
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_DRC>, <&ccu CLK_DRC>,
<&ccu CLK_DRAM_DRC>;
clock-names = "ahb", "mod", "ram";
resets = <&ccu RST_BUS_DRC>;
assigned-clocks = <&ccu CLK_DRC>;
assigned-clock-rates = <300000000>;
ports {
#address-cells = <1>;
#size-cells = <0>;
drc0_in: port@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
drc0_in_be0: endpoint@0 {
reg = <0>;
remote-endpoint = <&be0_out_drc0>;
};
};
drc0_out: port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
drc0_out_tcon0: endpoint@0 {
reg = <0>;
remote-endpoint = <&tcon0_in_drc0>;
};
};
};
};
};
thermal-zones {
@ -524,10 +368,37 @@
};
};
&be0 {
compatible = "allwinner,sun8i-a33-display-backend";
/* A33 has an extra "SAT" module packed inside the display backend */
reg = <0x01e60000 0x10000>, <0x01e80000 0x1000>;
reg-names = "be", "sat";
clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>,
<&ccu CLK_DRAM_DE_BE>, <&ccu CLK_BUS_SAT>;
clock-names = "ahb", "mod",
"ram", "sat";
resets = <&ccu RST_BUS_DE_BE>, <&ccu RST_BUS_SAT>;
reset-names = "be", "sat";
assigned-clocks = <&ccu CLK_DE_BE>;
assigned-clock-rates = <300000000>;
};
&ccu {
compatible = "allwinner,sun8i-a33-ccu";
};
&de {
compatible = "allwinner,sun8i-a33-display-engine";
};
&drc0 {
compatible = "allwinner,sun8i-a33-drc";
};
&fe0 {
compatible = "allwinner,sun8i-a33-display-frontend";
};
&mali {
operating-points-v2 = <&mali_opp_table>;
};
@ -544,6 +415,17 @@
};
&tcon0 {
compatible = "allwinner,sun8i-a33-tcon";
};
&tcon0_out {
tcon0_out_dsi: endpoint@1 {
reg = <1>;
remote-endpoint = <&dsi_in_tcon0>;
};
};
&usb_otg {
compatible = "allwinner,sun8i-a33-musb";
};

37
arch/arm/boot/dts/sun8i-q8-common.dtsi
View File

@ -49,6 +49,26 @@
ethernet0 = &sdio_wifi;
};
panel: panel {
/* Tablet dts should provide panel compatible */
backlight = <&backlight>;
enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */
power-supply = <&reg_dc1sw>;
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
panel_input: endpoint@0 {
reg = <0>;
remote-endpoint = <&tcon0_out_lcd>;
};
};
};
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
/*
@ -64,6 +84,10 @@
};
};
&de {
status = "okay";
};
&ehci0 {
status = "okay";
};
@ -90,6 +114,19 @@
};
};
&tcon0 {
pinctrl-names = "default";
pinctrl-0 = <&lcd_rgb666_pins>;
status = "okay";
};
&tcon0_out {
tcon0_out_lcd: endpoint@0 {
reg = <0>;
remote-endpoint = <&panel_input>;
};
};
&usbphy {
usb1_vbus-supply = <&reg_dldo1>;
};

41
arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
View File

@ -102,6 +102,8 @@
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&pio 6 10 GPIO_ACTIVE_LOW>; /* PG10 WIFI_EN */
clocks = <&ccu CLK_OUTA>;
clock-names = "ext_clock";
};
};
@ -196,6 +198,11 @@
status = "okay";
};
&pio {
pinctrl-names = "default";
pinctrl-0 = <&clk_out_a_pin>;
};
&reg_aldo2 {
regulator-always-on;
regulator-min-microvolt = <2500000>;
@ -250,12 +257,27 @@
regulator-name = "vcc-wifi-io";
};
/*
* Our WiFi chip needs both DLDO2 and DLDO3 to be powered at the same
* time, with the two being in sync, to be able to meet maximum power
* consumption during transmits. Since this is not really supported
* right now, just use the two as always on, and we will fix it later.
*/
&reg_dldo2 {
regulator-always-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc-wifi";
};
&reg_dldo3 {
regulator-always-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc-wifi-2";
};
&reg_dldo4 {
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
@ -278,6 +300,25 @@
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&uart3_pg_pins>, <&uart3_rts_cts_pg_pins>;
uart-has-rtscts;
status = "okay";
bluetooth {
compatible = "brcm,bcm43438-bt";
clocks = <&ccu CLK_OUTA>;
clock-names = "lpo";
vbat-supply = <&reg_dldo2>;
vddio-supply = <&reg_dldo1>;
device-wakeup-gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>; /* PG11 */
/* TODO host wake line connected to PMIC GPIO pins */
shutdown-gpios = <&pio 7 12 GPIO_ACTIVE_HIGH>; /* PH12 */
max-speed = <1500000>;
};
};
&usbphy {
usb1_vbus-supply = <&reg_vcc5v0>;
usb2_vbus-supply = <&reg_vcc5v0>;

15
arch/arm/boot/dts/sun8i-r40.dtsi
View File

@ -342,6 +342,11 @@
#interrupt-cells = <3>;
#gpio-cells = <3>;
clk_out_a_pin: clk-out-a-pin {
pins = "PI12";
function = "clk_out_a";
};
gmac_rgmii_pins: gmac-rgmii-pins {
pins = "PA0", "PA1", "PA2", "PA3",
"PA4", "PA5", "PA6", "PA7",
@ -389,6 +394,16 @@
pins = "PB22", "PB23";
function = "uart0";
};
uart3_pg_pins: uart3-pg-pins {
pins = "PG6", "PG7";
function = "uart3";
};
uart3_rts_cts_pg_pins: uart3-rts-cts-pg-pins {
pins = "PG8", "PG9";
function = "uart3";
};
};
wdt: watchdog@1c20c90 {

14
arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi
View File

@ -103,6 +103,8 @@
compatible = "mmc-pwrseq-simple";
pinctrl-names = "default";
reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
clocks = <&rtc 1>;
clock-names = "ext_clock";
};
};
@ -215,7 +217,19 @@
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
uart-has-rtscts;
status = "okay";
bluetooth {
compatible = "brcm,bcm43438-bt";
clocks = <&rtc 1>;
clock-names = "lpo";
vbat-supply = <&reg_vcc3v3>;
vddio-supply = <&reg_vcc3v3>;
device-wakeup-gpios = <&pio 6 13 GPIO_ACTIVE_HIGH>; /* PG13 */
host-wakeup-gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>; /* PG11 */
shutdown-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
};
};
&usb_otg {