forked from Minki/linux
viafb: prepare for PLL separation
This patch splits some functionality to extra functions. Signed-off-by: Florian Tobias Schandinat <FlorianSchandinat@gmx.de>
This commit is contained in:
Florian Tobias Schandinat
parent
1606f87e98
commit
0f77d4a052
@ -1430,6 +1430,70 @@ static u32 vx855_encode_pll(struct pll_config pll)
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| pll.multiplier;
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}
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static inline void cle266_set_primary_pll_encoded(u32 data)
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{
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via_write_reg_mask(VIASR, 0x40, 0x02, 0x02); /* enable reset */
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via_write_reg(VIASR, 0x46, data & 0xFF);
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via_write_reg(VIASR, 0x47, (data >> 8) & 0xFF);
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via_write_reg_mask(VIASR, 0x40, 0x00, 0x02); /* disable reset */
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}
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static inline void k800_set_primary_pll_encoded(u32 data)
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{
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via_write_reg_mask(VIASR, 0x40, 0x02, 0x02); /* enable reset */
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via_write_reg(VIASR, 0x44, data & 0xFF);
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via_write_reg(VIASR, 0x45, (data >> 8) & 0xFF);
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via_write_reg(VIASR, 0x46, (data >> 16) & 0xFF);
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via_write_reg_mask(VIASR, 0x40, 0x00, 0x02); /* disable reset */
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}
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static inline void cle266_set_secondary_pll_encoded(u32 data)
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{
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via_write_reg_mask(VIASR, 0x40, 0x04, 0x04); /* enable reset */
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via_write_reg(VIASR, 0x44, data & 0xFF);
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via_write_reg(VIASR, 0x45, (data >> 8) & 0xFF);
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via_write_reg_mask(VIASR, 0x40, 0x00, 0x04); /* disable reset */
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}
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static inline void k800_set_secondary_pll_encoded(u32 data)
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{
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via_write_reg_mask(VIASR, 0x40, 0x04, 0x04); /* enable reset */
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via_write_reg(VIASR, 0x4A, data & 0xFF);
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via_write_reg(VIASR, 0x4B, (data >> 8) & 0xFF);
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via_write_reg(VIASR, 0x4C, (data >> 16) & 0xFF);
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via_write_reg_mask(VIASR, 0x40, 0x00, 0x04); /* disable reset */
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}
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static void cle266_set_primary_pll(struct pll_config config)
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{
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cle266_set_primary_pll_encoded(cle266_encode_pll(config));
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}
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static void k800_set_primary_pll(struct pll_config config)
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{
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k800_set_primary_pll_encoded(k800_encode_pll(config));
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}
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static void vx855_set_primary_pll(struct pll_config config)
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{
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k800_set_primary_pll_encoded(vx855_encode_pll(config));
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}
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static void cle266_set_secondary_pll(struct pll_config config)
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{
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cle266_set_secondary_pll_encoded(cle266_encode_pll(config));
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}
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static void k800_set_secondary_pll(struct pll_config config)
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{
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k800_set_secondary_pll_encoded(k800_encode_pll(config));
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}
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static void vx855_set_secondary_pll(struct pll_config config)
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{
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k800_set_secondary_pll_encoded(vx855_encode_pll(config));
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}
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static inline u32 get_pll_internal_frequency(u32 ref_freq,
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struct pll_config pll)
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{
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@ -1474,21 +1538,21 @@ static struct pll_config get_pll_config(struct pll_limit *limits, int size,
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return best;
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}
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static u32 viafb_get_clk_value(int clk)
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static struct pll_config get_best_pll_config(int clk)
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{
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u32 value = 0;
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struct pll_config config;
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switch (viaparinfo->chip_info->gfx_chip_name) {
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case UNICHROME_CLE266:
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case UNICHROME_K400:
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value = cle266_encode_pll(get_pll_config(cle266_pll_limits,
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ARRAY_SIZE(cle266_pll_limits), clk));
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config = get_pll_config(cle266_pll_limits,
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ARRAY_SIZE(cle266_pll_limits), clk);
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break;
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case UNICHROME_K800:
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case UNICHROME_PM800:
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case UNICHROME_CN700:
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value = k800_encode_pll(get_pll_config(k800_pll_limits,
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ARRAY_SIZE(k800_pll_limits), clk));
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config = get_pll_config(k800_pll_limits,
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ARRAY_SIZE(k800_pll_limits), clk);
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break;
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case UNICHROME_CX700:
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case UNICHROME_CN750:
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@ -1496,38 +1560,31 @@ static u32 viafb_get_clk_value(int clk)
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case UNICHROME_P4M890:
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case UNICHROME_P4M900:
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case UNICHROME_VX800:
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value = k800_encode_pll(get_pll_config(cx700_pll_limits,
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ARRAY_SIZE(cx700_pll_limits), clk));
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config = get_pll_config(cx700_pll_limits,
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ARRAY_SIZE(cx700_pll_limits), clk);
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break;
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case UNICHROME_VX855:
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case UNICHROME_VX900:
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value = vx855_encode_pll(get_pll_config(vx855_pll_limits,
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ARRAY_SIZE(vx855_pll_limits), clk));
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config = get_pll_config(vx855_pll_limits,
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ARRAY_SIZE(vx855_pll_limits), clk);
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break;
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}
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return value;
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return config;
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}
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/* Set VCLK*/
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void viafb_set_vclock(u32 clk, int set_iga)
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{
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u32 value = viafb_get_clk_value(clk);
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DEBUG_MSG(KERN_INFO "PLL=0x%x", value);
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/* H.W. Reset : ON */
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viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7);
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struct pll_config config = get_best_pll_config(clk);
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if (set_iga == IGA1) {
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/* Change D,N FOR VCLK */
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switch (viaparinfo->chip_info->gfx_chip_name) {
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case UNICHROME_CLE266:
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case UNICHROME_K400:
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via_write_reg(VIASR, SR46, (value & 0x00FF));
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via_write_reg(VIASR, SR47, (value & 0xFF00) >> 8);
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cle266_set_primary_pll(config);
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break;
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case UNICHROME_K800:
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case UNICHROME_PM800:
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case UNICHROME_CN700:
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@ -1537,11 +1594,11 @@ void viafb_set_vclock(u32 clk, int set_iga)
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case UNICHROME_P4M890:
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case UNICHROME_P4M900:
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case UNICHROME_VX800:
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k800_set_primary_pll(config);
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break;
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case UNICHROME_VX855:
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case UNICHROME_VX900:
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via_write_reg(VIASR, SR44, (value & 0x0000FF));
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via_write_reg(VIASR, SR45, (value & 0x00FF00) >> 8);
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via_write_reg(VIASR, SR46, (value & 0xFF0000) >> 16);
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vx855_set_primary_pll(config);
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break;
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}
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}
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@ -1551,10 +1608,8 @@ void viafb_set_vclock(u32 clk, int set_iga)
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switch (viaparinfo->chip_info->gfx_chip_name) {
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case UNICHROME_CLE266:
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case UNICHROME_K400:
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via_write_reg(VIASR, SR44, (value & 0x00FF));
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via_write_reg(VIASR, SR45, (value & 0xFF00) >> 8);
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cle266_set_secondary_pll(config);
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break;
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case UNICHROME_K800:
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case UNICHROME_PM800:
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case UNICHROME_CN700:
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@ -1564,29 +1619,15 @@ void viafb_set_vclock(u32 clk, int set_iga)
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case UNICHROME_P4M890:
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case UNICHROME_P4M900:
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case UNICHROME_VX800:
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k800_set_secondary_pll(config);
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break;
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case UNICHROME_VX855:
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case UNICHROME_VX900:
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via_write_reg(VIASR, SR4A, (value & 0x0000FF));
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via_write_reg(VIASR, SR4B, (value & 0x00FF00) >> 8);
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via_write_reg(VIASR, SR4C, (value & 0xFF0000) >> 16);
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vx855_set_secondary_pll(config);
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break;
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}
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}
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/* H.W. Reset : OFF */
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viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7);
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/* Reset PLL */
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if (set_iga == IGA1) {
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viafb_write_reg_mask(SR40, VIASR, 0x02, BIT1);
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viafb_write_reg_mask(SR40, VIASR, 0x00, BIT1);
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}
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if (set_iga == IGA2) {
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viafb_write_reg_mask(SR40, VIASR, 0x04, BIT2);
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viafb_write_reg_mask(SR40, VIASR, 0x00, BIT2);
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}
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/* Fire! */
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via_write_misc_reg_mask(0x0C, 0x0C); /* select external clock */
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}
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