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drm/amdgpu: Flush TLB after mapping for VG20+XGMI

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For VG20 + XGMI bridge, all mappings PTEs cache in TC, this may have
stall invalid PTEs in TC because one cache line has 8 pages. Need always
flush_tlb after updating mapping.

Signed-off-by: Philip Yang <Philip.Yang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Philip Yang 2022-04-01 15:30:12 -04:00 committed by Alex Deucher
parent 34452ac303
commit 0f12a22f37
1 changed files with 6 additions and 0 deletions
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6
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
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@ -837,6 +837,12 @@ int amdgpu_vm_update_range(struct amdgpu_device *adev, struct amdgpu_vm *vm,
goto error_unlock;
}
/* Vega20+XGMI where PTEs get inadvertently cached in L2 texture cache,
* heavy-weight flush TLB unconditionally.
*/
flush_tlb |= adev->gmc.xgmi.num_physical_nodes &&
adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 0);
memset(&params, 0, sizeof(params));
params.adev = adev;
params.vm = vm;