forked from Minki/linux
clk: renesas: rcar-gen3: Allow changing the RPC[D2] clocks
I was unable to get clk_set_rate() setting a lower RPC-IF clock frequency
and that issue boiled down to me not passing CLK_SET_RATE_PARENT flag to
clk_register_composite() when registering the RPC[D2] clocks...
Fixes: db4a0073cc
("clk: renesas: rcar-gen3: Add RPC clocks")
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Link: https://lore.kernel.org/r/be27a344-d8bf-9e0c-8950-2d1b48498496@cogentembedded.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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parent
03975b72b4
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@ -470,7 +470,8 @@ static struct clk * __init cpg_rpc_clk_register(const char *name,
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clk = clk_register_composite(NULL, name, &parent_name, 1, NULL, NULL,
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&rpc->div.hw, &clk_divider_ops,
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&rpc->gate.hw, &clk_gate_ops, 0);
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&rpc->gate.hw, &clk_gate_ops,
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CLK_SET_RATE_PARENT);
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if (IS_ERR(clk)) {
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kfree(rpc);
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return clk;
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@ -506,7 +507,8 @@ static struct clk * __init cpg_rpcd2_clk_register(const char *name,
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clk = clk_register_composite(NULL, name, &parent_name, 1, NULL, NULL,
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&rpcd2->fixed.hw, &clk_fixed_factor_ops,
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&rpcd2->gate.hw, &clk_gate_ops, 0);
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&rpcd2->gate.hw, &clk_gate_ops,
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CLK_SET_RATE_PARENT);
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if (IS_ERR(clk))
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kfree(rpcd2);
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