drm/i915/gt: Order GT registers by MMIO offset

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The random order of register definitions we have today causes a lot of
confusion and unintentional duplication when new registers/bits are
added to the driver.  Let's order the GT register file by MMIO offset

A couple duplicated/unused register definitions are dropped while doing
this re-order:  GEN11_GT_INTR_DW{0,1}, GEN11_IIR_REG{0,1}_SELECTOR, and
GEN11_INTR_IDENTITY_REG{0,1} aren't used anywhere in the driver because
we have other parameterized macros referencing those registers.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220209051140.1599643-7-matthew.d.roper@intel.com

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This commit is contained in:

Matt Roper 2022-02-08 21:11:40 -08:00

parent bd3de31950

commit 0d53879faa

1 changed files with 1137 additions and 1132 deletions

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drivers/gpu/drm/i915/gt/intel_gt_regs.h

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