forked from Minki/linux
ARM: kprobes: Infrastructure for table driven decoding of CPU instructions
The existing ARM instruction decoding functions are a mass of if/else code. Rather than follow this pattern for Thumb instruction decoding this patch implements an infrastructure for a new table driven scheme. This has several advantages: - Reduces the kernel size by approx 2kB. (The ARM instruction decoding will eventually have -3.1kB code, +1.3kB data; with similar or better estimated savings for Thumb decoding.) - Allows programmatic checking of decoding consistency and test case coverage. - Provides more uniform source code and is therefore, arguably, clearer. For a detailed explanation of how decoding tables work see the in-source documentation in kprobes.h, and also for kprobe_decode_insn(). Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
This commit is contained in:
Jon Medhurst
Tixy
parent
e2960317d4
commit
0d1a095aa1
@ -140,3 +140,261 @@ kprobe_check_cc * const kprobe_condition_checks[16] = {
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&__check_hi, &__check_ls, &__check_ge, &__check_lt,
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&__check_gt, &__check_le, &__check_al, &__check_al
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};
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/*
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* Prepare an instruction slot to receive an instruction for emulating.
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* This is done by placing a subroutine return after the location where the
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* instruction will be placed. We also modify ARM instructions to be
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* unconditional as the condition code will already be checked before any
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* emulation handler is called.
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*/
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static kprobe_opcode_t __kprobes
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prepare_emulated_insn(kprobe_opcode_t insn, struct arch_specific_insn *asi,
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bool thumb)
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{
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#ifdef CONFIG_THUMB2_KERNEL
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if (thumb) {
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u16 *thumb_insn = (u16 *)asi->insn;
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thumb_insn[1] = 0x4770; /* Thumb bx lr */
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thumb_insn[2] = 0x4770; /* Thumb bx lr */
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return insn;
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}
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asi->insn[1] = 0xe12fff1e; /* ARM bx lr */
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#else
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asi->insn[1] = 0xe1a0f00e; /* mov pc, lr */
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#endif
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/* Make an ARM instruction unconditional */
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if (insn < 0xe0000000)
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insn = (insn | 0xe0000000) & ~0x10000000;
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return insn;
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}
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/*
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* Write a (probably modified) instruction into the slot previously prepared by
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* prepare_emulated_insn
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*/
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static void __kprobes
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set_emulated_insn(kprobe_opcode_t insn, struct arch_specific_insn *asi,
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bool thumb)
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{
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#ifdef CONFIG_THUMB2_KERNEL
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if (thumb) {
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u16 *ip = (u16 *)asi->insn;
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if (is_wide_instruction(insn))
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*ip++ = insn >> 16;
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*ip++ = insn;
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return;
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}
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#endif
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asi->insn[0] = insn;
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}
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/*
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* When we modify the register numbers encoded in an instruction to be emulated,
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* the new values come from this define. For ARM and 32-bit Thumb instructions
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* this gives...
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*
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* bit position 16 12 8 4 0
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* ---------------+---+---+---+---+---+
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* register r2 r0 r1 -- r3
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*/
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#define INSN_NEW_BITS 0x00020103
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/* Each nibble has same value as that at INSN_NEW_BITS bit 16 */
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#define INSN_SAMEAS16_BITS 0x22222222
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/*
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* Validate and modify each of the registers encoded in an instruction.
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*
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* Each nibble in regs contains a value from enum decode_reg_type. For each
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* non-zero value, the corresponding nibble in pinsn is validated and modified
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* according to the type.
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*/
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static bool __kprobes decode_regs(kprobe_opcode_t* pinsn, u32 regs)
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{
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kprobe_opcode_t insn = *pinsn;
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kprobe_opcode_t mask = 0xf; /* Start at least significant nibble */
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for (; regs != 0; regs >>= 4, mask <<= 4) {
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kprobe_opcode_t new_bits = INSN_NEW_BITS;
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switch (regs & 0xf) {
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case REG_TYPE_NONE:
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/* Nibble not a register, skip to next */
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continue;
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case REG_TYPE_ANY:
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/* Any register is allowed */
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break;
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case REG_TYPE_SAMEAS16:
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/* Replace register with same as at bit position 16 */
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new_bits = INSN_SAMEAS16_BITS;
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break;
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case REG_TYPE_SP:
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/* Only allow SP (R13) */
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if ((insn ^ 0xdddddddd) & mask)
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goto reject;
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break;
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case REG_TYPE_PC:
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/* Only allow PC (R15) */
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if ((insn ^ 0xffffffff) & mask)
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goto reject;
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break;
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case REG_TYPE_NOSP:
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/* Reject SP (R13) */
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if (((insn ^ 0xdddddddd) & mask) == 0)
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goto reject;
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break;
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case REG_TYPE_NOSPPC:
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case REG_TYPE_NOSPPCX:
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/* Reject SP and PC (R13 and R15) */
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if (((insn ^ 0xdddddddd) & 0xdddddddd & mask) == 0)
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goto reject;
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break;
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case REG_TYPE_NOPCWB:
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if (!is_writeback(insn))
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break; /* No writeback, so any register is OK */
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/* fall through... */
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case REG_TYPE_NOPC:
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case REG_TYPE_NOPCX:
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/* Reject PC (R15) */
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if (((insn ^ 0xffffffff) & mask) == 0)
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goto reject;
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break;
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}
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/* Replace value of nibble with new register number... */
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insn &= ~mask;
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insn |= new_bits & mask;
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}
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*pinsn = insn;
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return true;
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reject:
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return false;
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}
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static const int decode_struct_sizes[NUM_DECODE_TYPES] = {
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[DECODE_TYPE_TABLE] = sizeof(struct decode_table),
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[DECODE_TYPE_CUSTOM] = sizeof(struct decode_custom),
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[DECODE_TYPE_SIMULATE] = sizeof(struct decode_simulate),
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[DECODE_TYPE_EMULATE] = sizeof(struct decode_emulate),
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[DECODE_TYPE_OR] = sizeof(struct decode_or),
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[DECODE_TYPE_REJECT] = sizeof(struct decode_reject)
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};
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/*
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* kprobe_decode_insn operates on data tables in order to decode an ARM
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* architecture instruction onto which a kprobe has been placed.
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*
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* These instruction decoding tables are a concatenation of entries each
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* of which consist of one of the following structs:
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*
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* decode_table
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* decode_custom
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* decode_simulate
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* decode_emulate
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* decode_or
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* decode_reject
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*
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* Each of these starts with a struct decode_header which has the following
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* fields:
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*
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* type_regs
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* mask
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* value
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*
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* The least significant DECODE_TYPE_BITS of type_regs contains a value
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* from enum decode_type, this indicates which of the decode_* structs
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* the entry contains. The value DECODE_TYPE_END indicates the end of the
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* table.
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*
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* When the table is parsed, each entry is checked in turn to see if it
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* matches the instruction to be decoded using the test:
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*
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* (insn & mask) == value
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*
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* If no match is found before the end of the table is reached then decoding
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* fails with INSN_REJECTED.
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*
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* When a match is found, decode_regs() is called to validate and modify each
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* of the registers encoded in the instruction; the data it uses to do this
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* is (type_regs >> DECODE_TYPE_BITS). A validation failure will cause decoding
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* to fail with INSN_REJECTED.
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*
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* Once the instruction has passed the above tests, further processing
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* depends on the type of the table entry's decode struct.
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*
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*/
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int __kprobes
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kprobe_decode_insn(kprobe_opcode_t insn, struct arch_specific_insn *asi,
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const union decode_item *table, bool thumb)
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{
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const struct decode_header *h = (struct decode_header *)table;
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const struct decode_header *next;
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bool matched = false;
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insn = prepare_emulated_insn(insn, asi, thumb);
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for (;; h = next) {
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enum decode_type type = h->type_regs.bits & DECODE_TYPE_MASK;
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u32 regs = h->type_regs.bits >> DECODE_TYPE_BITS;
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if (type == DECODE_TYPE_END)
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return INSN_REJECTED;
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next = (struct decode_header *)
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((uintptr_t)h + decode_struct_sizes[type]);
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if (!matched && (insn & h->mask.bits) != h->value.bits)
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continue;
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if (!decode_regs(&insn, regs))
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return INSN_REJECTED;
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switch (type) {
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case DECODE_TYPE_TABLE: {
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struct decode_table *d = (struct decode_table *)h;
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next = (struct decode_header *)d->table.table;
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break;
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}
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case DECODE_TYPE_CUSTOM: {
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struct decode_custom *d = (struct decode_custom *)h;
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return (*d->decoder.decoder)(insn, asi);
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}
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case DECODE_TYPE_SIMULATE: {
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struct decode_simulate *d = (struct decode_simulate *)h;
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asi->insn_handler = d->handler.handler;
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return INSN_GOOD_NO_SLOT;
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}
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case DECODE_TYPE_EMULATE: {
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struct decode_emulate *d = (struct decode_emulate *)h;
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asi->insn_handler = d->handler.handler;
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set_emulated_insn(insn, asi, thumb);
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return INSN_GOOD;
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}
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case DECODE_TYPE_OR:
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matched = true;
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break;
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case DECODE_TYPE_REJECT:
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default:
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return INSN_REJECTED;
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}
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}
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}
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@ -1,7 +1,9 @@
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/*
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* arch/arm/kernel/kprobes.h
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*
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* Contents moved from arch/arm/include/asm/kprobes.h which is
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* Copyright (C) 2011 Jon Medhurst <tixy@yxit.co.uk>.
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*
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* Some contents moved here from arch/arm/include/asm/kprobes.h which is
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* Copyright (C) 2006, 2007 Motorola Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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@ -99,4 +101,248 @@ static inline unsigned long it_advance(unsigned long cpsr)
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*/
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#define is_writeback(insn) ((insn ^ 0x01000000) & 0x01200000)
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/*
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* The following definitions and macros are used to build instruction
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* decoding tables for use by kprobe_decode_insn.
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*
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* These tables are a concatenation of entries each of which consist of one of
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* the decode_* structs. All of the fields in every type of decode structure
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* are of the union type decode_item, therefore the entire decode table can be
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* viewed as an array of these and declared like:
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*
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* static const union decode_item table_name[] = {};
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*
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* In order to construct each entry in the table, macros are used to
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* initialise a number of sequential decode_item values in a layout which
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* matches the relevant struct. E.g. DECODE_SIMULATE initialise a struct
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* decode_simulate by initialising four decode_item objects like this...
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*
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* {.bits = _type},
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* {.bits = _mask},
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* {.bits = _value},
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* {.handler = _handler},
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*
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* Initialising a specified member of the union means that the compiler
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* will produce a warning if the argument is of an incorrect type.
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*
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* Below is a list of each of the macros used to initialise entries and a
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* description of the action performed when that entry is matched to an
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* instruction. A match is found when (instruction & mask) == value.
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*
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* DECODE_TABLE(mask, value, table)
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* Instruction decoding jumps to parsing the new sub-table 'table'.
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*
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* DECODE_CUSTOM(mask, value, decoder)
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* The custom function 'decoder' is called to the complete decoding
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* of an instruction.
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*
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* DECODE_SIMULATE(mask, value, handler)
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* Set the probes instruction handler to 'handler', this will be used
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* to simulate the instruction when the probe is hit. Decoding returns
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* with INSN_GOOD_NO_SLOT.
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*
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* DECODE_EMULATE(mask, value, handler)
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* Set the probes instruction handler to 'handler', this will be used
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* to emulate the instruction when the probe is hit. The modified
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* instruction (see below) is placed in the probes instruction slot so it
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* may be called by the emulation code. Decoding returns with INSN_GOOD.
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*
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* DECODE_REJECT(mask, value)
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* Instruction decoding fails with INSN_REJECTED
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*
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* DECODE_OR(mask, value)
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* This allows the mask/value test of multiple table entries to be
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* logically ORed. Once an 'or' entry is matched the decoding action to
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* be performed is that of the next entry which isn't an 'or'. E.g.
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*
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* DECODE_OR (mask1, value1)
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* DECODE_OR (mask2, value2)
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* DECODE_SIMULATE (mask3, value3, simulation_handler)
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*
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* This means that if any of the three mask/value pairs match the
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* instruction being decoded, then 'simulation_handler' will be used
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* for it.
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*
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* Both the SIMULATE and EMULATE macros have a second form which take an
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* additional 'regs' argument.
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*
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* DECODE_SIMULATEX(mask, value, handler, regs)
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* DECODE_EMULATEX (mask, value, handler, regs)
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*
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* These are used to specify what kind of CPU register is encoded in each of the
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* least significant 5 nibbles of the instruction being decoded. The regs value
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* is specified using the REGS macro, this takes any of the REG_TYPE_* values
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* from enum decode_reg_type as arguments; only the '*' part of the name is
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* given. E.g.
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*
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* REGS(0, ANY, NOPC, 0, ANY)
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*
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* This indicates an instruction is encoded like:
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*
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* bits 19..16 ignore
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* bits 15..12 any register allowed here
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* bits 11.. 8 any register except PC allowed here
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* bits 7.. 4 ignore
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* bits 3.. 0 any register allowed here
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*
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* This register specification is checked after a decode table entry is found to
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* match an instruction (through the mask/value test). Any invalid register then
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* found in the instruction will cause decoding to fail with INSN_REJECTED. In
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* the above example this would happen if bits 11..8 of the instruction were
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* 1111, indicating R15 or PC.
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*
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* As well as checking for legal combinations of registers, this data is also
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* used to modify the registers encoded in the instructions so that an
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* emulation routines can use it. (See decode_regs() and INSN_NEW_BITS.)
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*
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* Here is a real example which matches ARM instructions of the form
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* "AND <Rd>,<Rn>,<Rm>,<shift> <Rs>"
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*
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* DECODE_EMULATEX (0x0e000090, 0x00000010, emulate_rd12rn16rm0rs8_rwflags,
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* REGS(ANY, ANY, NOPC, 0, ANY)),
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* ^ ^ ^ ^
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* Rn Rd Rs Rm
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*
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* Decoding the instruction "AND R4, R5, R6, ASL R15" will be rejected because
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* Rs == R15
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*
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* Decoding the instruction "AND R4, R5, R6, ASL R7" will be accepted and the
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* instruction will be modified to "AND R0, R2, R3, ASL R1" and then placed into
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* the kprobes instruction slot. This can then be called later by the handler
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* function emulate_rd12rn16rm0rs8_rwflags in order to simulate the instruction.
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*/
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enum decode_type {
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DECODE_TYPE_END,
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DECODE_TYPE_TABLE,
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DECODE_TYPE_CUSTOM,
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DECODE_TYPE_SIMULATE,
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DECODE_TYPE_EMULATE,
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DECODE_TYPE_OR,
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DECODE_TYPE_REJECT,
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NUM_DECODE_TYPES /* Must be last enum */
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};
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#define DECODE_TYPE_BITS 4
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#define DECODE_TYPE_MASK ((1 << DECODE_TYPE_BITS) - 1)
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enum decode_reg_type {
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REG_TYPE_NONE = 0, /* Not a register, ignore */
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REG_TYPE_ANY, /* Any register allowed */
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REG_TYPE_SAMEAS16, /* Register should be same as that at bits 19..16 */
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REG_TYPE_SP, /* Register must be SP */
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REG_TYPE_PC, /* Register must be PC */
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REG_TYPE_NOSP, /* Register must not be SP */
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REG_TYPE_NOSPPC, /* Register must not be SP or PC */
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REG_TYPE_NOPC, /* Register must not be PC */
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REG_TYPE_NOPCWB, /* No PC if load/store write-back flag also set */
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/* The following types are used when the encoding for PC indicates
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* another instruction form. This distiction only matters for test
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* case coverage checks.
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*/
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REG_TYPE_NOPCX, /* Register must not be PC */
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REG_TYPE_NOSPPCX, /* Register must not be SP or PC */
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/* Alias to allow '0' arg to be used in REGS macro. */
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REG_TYPE_0 = REG_TYPE_NONE
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};
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#define REGS(r16, r12, r8, r4, r0) \
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((REG_TYPE_##r16) << 16) + \
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((REG_TYPE_##r12) << 12) + \
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((REG_TYPE_##r8) << 8) + \
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((REG_TYPE_##r4) << 4) + \
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(REG_TYPE_##r0)
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union decode_item {
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u32 bits;
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const union decode_item *table;
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kprobe_insn_handler_t *handler;
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kprobe_decode_insn_t *decoder;
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};
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#define DECODE_END \
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{.bits = DECODE_TYPE_END}
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struct decode_header {
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union decode_item type_regs;
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union decode_item mask;
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union decode_item value;
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};
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||||
|
||||
#define DECODE_HEADER(_type, _mask, _value, _regs) \
|
||||
{.bits = (_type) | ((_regs) << DECODE_TYPE_BITS)}, \
|
||||
{.bits = (_mask)}, \
|
||||
{.bits = (_value)}
|
||||
|
||||
|
||||
struct decode_table {
|
||||
struct decode_header header;
|
||||
union decode_item table;
|
||||
};
|
||||
|
||||
#define DECODE_TABLE(_mask, _value, _table) \
|
||||
DECODE_HEADER(DECODE_TYPE_TABLE, _mask, _value, 0), \
|
||||
{.table = (_table)}
|
||||
|
||||
|
||||
struct decode_custom {
|
||||
struct decode_header header;
|
||||
union decode_item decoder;
|
||||
};
|
||||
|
||||
#define DECODE_CUSTOM(_mask, _value, _decoder) \
|
||||
DECODE_HEADER(DECODE_TYPE_CUSTOM, _mask, _value, 0), \
|
||||
{.decoder = (_decoder)}
|
||||
|
||||
|
||||
struct decode_simulate {
|
||||
struct decode_header header;
|
||||
union decode_item handler;
|
||||
};
|
||||
|
||||
#define DECODE_SIMULATEX(_mask, _value, _handler, _regs) \
|
||||
DECODE_HEADER(DECODE_TYPE_SIMULATE, _mask, _value, _regs), \
|
||||
{.handler = (_handler)}
|
||||
|
||||
#define DECODE_SIMULATE(_mask, _value, _handler) \
|
||||
DECODE_SIMULATEX(_mask, _value, _handler, 0)
|
||||
|
||||
|
||||
struct decode_emulate {
|
||||
struct decode_header header;
|
||||
union decode_item handler;
|
||||
};
|
||||
|
||||
#define DECODE_EMULATEX(_mask, _value, _handler, _regs) \
|
||||
DECODE_HEADER(DECODE_TYPE_EMULATE, _mask, _value, _regs), \
|
||||
{.handler = (_handler)}
|
||||
|
||||
#define DECODE_EMULATE(_mask, _value, _handler) \
|
||||
DECODE_EMULATEX(_mask, _value, _handler, 0)
|
||||
|
||||
|
||||
struct decode_or {
|
||||
struct decode_header header;
|
||||
};
|
||||
|
||||
#define DECODE_OR(_mask, _value) \
|
||||
DECODE_HEADER(DECODE_TYPE_OR, _mask, _value, 0)
|
||||
|
||||
|
||||
struct decode_reject {
|
||||
struct decode_header header;
|
||||
};
|
||||
|
||||
#define DECODE_REJECT(_mask, _value) \
|
||||
DECODE_HEADER(DECODE_TYPE_REJECT, _mask, _value, 0)
|
||||
|
||||
|
||||
int kprobe_decode_insn(kprobe_opcode_t insn, struct arch_specific_insn *asi,
|
||||
const union decode_item *table, bool thumb16);
|
||||
|
||||
|
||||
#endif /* _ARM_KERNEL_KPROBES_H */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user