forked from Minki/linux
ASoC: Fix non-networked I2S mode for PXA SSP
Two issues are fixed here: - I2S transmits the left frame with the clock low but I don't seem to get LRCLK out without SFRMDLY being set so invert SFRMP and set a delay. - I2S has a clock cycle prior to the first data byte in each channel so we need to delay the data by one cycle. Tested-by: Daniel Mack <daniel@caiaq.de> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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@ -1,4 +1,3 @@
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#define DEBUG
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/*
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* pxa-ssp.c -- ALSA Soc Audio Layer
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*
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@ -561,14 +560,15 @@ static int pxa_ssp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
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sscr0 |= SSCR0_PSP;
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sscr1 |= SSCR1_RWOT | SSCR1_TRAIL;
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/* See hw_params() */
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switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
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case SND_SOC_DAIFMT_NB_NF:
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break;
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case SND_SOC_DAIFMT_NB_IF:
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sspsp |= SSPSP_SFRMP;
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break;
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case SND_SOC_DAIFMT_NB_IF:
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break;
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case SND_SOC_DAIFMT_IB_IF:
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sspsp |= SSPSP_SFRMP | SSPSP_SCMODE(3);
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sspsp |= SSPSP_SCMODE(3);
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break;
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default:
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return -EINVAL;
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@ -691,8 +691,17 @@ static int pxa_ssp_hw_params(struct snd_pcm_substream *substream,
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#else
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return -EINVAL;
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#endif
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} else
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sspsp |= SSPSP_SFRMWDTH(width);
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} else {
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/* The frame width is the width the LRCLK is
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* asserted for; the delay is expressed in
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* half cycle units. We need the extra cycle
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* because the data starts clocking out one BCLK
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* after LRCLK changes polarity.
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*/
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sspsp |= SSPSP_SFRMWDTH(width + 1);
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sspsp |= SSPSP_SFRMDLY((width + 1) * 2);
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sspsp |= SSPSP_DMYSTRT(1);
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}
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ssp_write_reg(ssp, SSPSP, sspsp);
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break;
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