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drm/amd/display: Expand DP module equalization API.

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[Why & How]
Add functionality useful for DP equalization phase of link training to
public interface.

Signed-off-by: Jimmy Kizito <Jimmy.Kizito@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Jimmy Kizito 2021-04-19 15:12:01 -04:00 committed by Alex Deucher
parent ae88357c79
commit 0cb1588571
2 changed files with 19 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

22
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
View File

@ -435,7 +435,7 @@ bool dp_is_cr_done(enum dc_lane_count ln_count,
return true; return true;
} }
static bool is_ch_eq_done(enum dc_lane_count ln_count, bool dp_is_ch_eq_done(enum dc_lane_count ln_count,
union lane_status *dpcd_lane_status) union lane_status *dpcd_lane_status)
{ {
bool done = true; bool done = true;
@ -446,7 +446,7 @@ static bool is_ch_eq_done(enum dc_lane_count ln_count,
return done; return done;
} }
static bool is_symbol_locked(enum dc_lane_count ln_count, bool dp_is_symbol_locked(enum dc_lane_count ln_count,
union lane_status *dpcd_lane_status) union lane_status *dpcd_lane_status)
{ {
bool locked = true; bool locked = true;
@ -457,7 +457,7 @@ static bool is_symbol_locked(enum dc_lane_count ln_count,
return locked; return locked;
} }
static inline bool is_interlane_aligned(union lane_align_status_updated align_status) bool dp_is_interlane_aligned(union lane_align_status_updated align_status)
{ {
return align_status.bits.INTERLANE_ALIGN_DONE == 1; return align_status.bits.INTERLANE_ALIGN_DONE == 1;
} }
@ -865,9 +865,9 @@ static bool perform_post_lt_adj_req_sequence(
if (!dp_is_cr_done(lane_count, dpcd_lane_status)) if (!dp_is_cr_done(lane_count, dpcd_lane_status))
return false; return false;
if (!is_ch_eq_done(lane_count, dpcd_lane_status) || if (!dp_is_ch_eq_done(lane_count, dpcd_lane_status) ||
!is_symbol_locked(lane_count, dpcd_lane_status) || !dp_is_symbol_locked(lane_count, dpcd_lane_status) ||
!is_interlane_aligned(dpcd_lane_status_updated)) !dp_is_interlane_aligned(dpcd_lane_status_updated))
return false; return false;
for (lane = 0; lane < (uint32_t)(lane_count); lane++) { for (lane = 0; lane < (uint32_t)(lane_count); lane++) {
@ -913,7 +913,7 @@ static bool perform_post_lt_adj_req_sequence(
} }
/* Only used for channel equalization */ /* Only used for channel equalization */
static uint32_t translate_training_aux_read_interval(uint32_t dpcd_aux_read_interval) uint32_t dp_translate_training_aux_read_interval(uint32_t dpcd_aux_read_interval)
{ {
unsigned int aux_rd_interval_us = 400; unsigned int aux_rd_interval_us = 400;
@ -998,7 +998,7 @@ static enum link_training_result perform_channel_equalization_sequence(
if (is_repeater(link, offset)) if (is_repeater(link, offset))
wait_time_microsec = wait_time_microsec =
translate_training_aux_read_interval( dp_translate_training_aux_read_interval(
link->dpcd_caps.lttpr_caps.aux_rd_interval[offset - 1]); link->dpcd_caps.lttpr_caps.aux_rd_interval[offset - 1]);
dp_wait_for_training_aux_rd_interval( dp_wait_for_training_aux_rd_interval(
@ -1021,9 +1021,9 @@ static enum link_training_result perform_channel_equalization_sequence(
return LINK_TRAINING_EQ_FAIL_CR; return LINK_TRAINING_EQ_FAIL_CR;
/* 6. check CHEQ done*/ /* 6. check CHEQ done*/
if (is_ch_eq_done(lane_count, dpcd_lane_status) && if (dp_is_ch_eq_done(lane_count, dpcd_lane_status) &&
is_symbol_locked(lane_count, dpcd_lane_status) && dp_is_symbol_locked(lane_count, dpcd_lane_status) &&
is_interlane_aligned(dpcd_lane_status_updated)) dp_is_interlane_aligned(dpcd_lane_status_updated))
return LINK_TRAINING_SUCCESS; return LINK_TRAINING_SUCCESS;
/* 7. update VS/PE/PC2 in lt_settings*/ /* 7. update VS/PE/PC2 in lt_settings*/

8
drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
View File

@ -130,6 +130,12 @@ bool dp_is_cr_done(enum dc_lane_count ln_count,
enum link_training_result dp_get_cr_failure(enum dc_lane_count ln_count, enum link_training_result dp_get_cr_failure(enum dc_lane_count ln_count,
union lane_status *dpcd_lane_status); union lane_status *dpcd_lane_status);
bool dp_is_ch_eq_done(enum dc_lane_count ln_count,
union lane_status *dpcd_lane_status);
bool dp_is_symbol_locked(enum dc_lane_count ln_count,
union lane_status *dpcd_lane_status);
bool dp_is_interlane_aligned(union lane_align_status_updated align_status);
bool dp_is_max_vs_reached( bool dp_is_max_vs_reached(
const struct link_training_settings *lt_settings); const struct link_training_settings *lt_settings);
@ -137,6 +143,8 @@ void dp_update_drive_settings(
struct link_training_settings *dest, struct link_training_settings *dest,
struct link_training_settings src); struct link_training_settings src);
uint32_t dp_translate_training_aux_read_interval(uint32_t dpcd_aux_read_interval);
enum dpcd_training_patterns enum dpcd_training_patterns
dc_dp_training_pattern_to_dpcd_training_pattern( dc_dp_training_pattern_to_dpcd_training_pattern(
struct dc_link *link, struct dc_link *link,