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clk: imx8mq: add GPIO clocks to clock tree

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i.MX8MQ has clock gate for each GPIO bank, add them
into clock tree for GPIO driver to manage.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Anson Huang 2019-02-27 01:28:26 +00:00 committed by Stephen Boyd
parent e9dda4af68
commit 0c91c11c7d
2 changed files with 12 additions and 1 deletions
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5
drivers/clk/imx/clk-imx8mq.c
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@ -473,6 +473,11 @@ static int imx8mq_clocks_probe(struct platform_device *pdev)
clks[IMX8MQ_CLK_ECSPI2_ROOT] = imx_clk_gate4("ecspi2_root_clk", "ecspi2", base + 0x4080, 0);
clks[IMX8MQ_CLK_ECSPI3_ROOT] = imx_clk_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090, 0);
clks[IMX8MQ_CLK_ENET1_ROOT] = imx_clk_gate4("enet1_root_clk", "enet_axi", base + 0x40a0, 0);
clks[IMX8MQ_CLK_GPIO1_ROOT] = imx_clk_gate4("gpio1_root_clk", "ipg_root", base + 0x40b0, 0);
clks[IMX8MQ_CLK_GPIO2_ROOT] = imx_clk_gate4("gpio2_root_clk", "ipg_root", base + 0x40c0, 0);
clks[IMX8MQ_CLK_GPIO3_ROOT] = imx_clk_gate4("gpio3_root_clk", "ipg_root", base + 0x40d0, 0);
clks[IMX8MQ_CLK_GPIO4_ROOT] = imx_clk_gate4("gpio4_root_clk", "ipg_root", base + 0x40e0, 0);
clks[IMX8MQ_CLK_GPIO5_ROOT] = imx_clk_gate4("gpio5_root_clk", "ipg_root", base + 0x40f0, 0);
clks[IMX8MQ_CLK_GPT1_ROOT] = imx_clk_gate4("gpt1_root_clk", "gpt1", base + 0x4100, 0);
clks[IMX8MQ_CLK_I2C1_ROOT] = imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0);
clks[IMX8MQ_CLK_I2C2_ROOT] = imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0);

8
include/dt-bindings/clock/imx8mq-clock.h
View File

@ -394,5 +394,11 @@
#define IMX8MQ_CLK_CLKO1 268
#define IMX8MQ_CLK_ARM 269
#define IMX8MQ_CLK_END 270
#define IMX8MQ_CLK_GPIO1_ROOT 270
#define IMX8MQ_CLK_GPIO2_ROOT 271
#define IMX8MQ_CLK_GPIO3_ROOT 272
#define IMX8MQ_CLK_GPIO4_ROOT 273
#define IMX8MQ_CLK_GPIO5_ROOT 274
#define IMX8MQ_CLK_END 275
#endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */