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based on exynos-dt-2 and s3c24xx-dt-2

Browse Source 
- use #include for all Samsung DT
 - add clk for exynos audio subsystem (audss) and i2s
 - support audss and i2s for exynos5250
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Merge tag 'common-clk-audio' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/drivers

From Kukjin Kim:

based on exynos-dt-2 and s3c24xx-dt-2
- use #include for all Samsung DT
- add clk for exynos audio subsystem (audss) and i2s
- support audss and i2s for exynos5250

* tag 'common-clk-audio' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
  clk: exynos5250: Add enum entries for divider clock of i2s1 and i2s2
  ARM: dts: Update Samsung I2S documentation
  ARM: dts: add clock provider information for i2s controllers in Exynos5250
  ARM: dts: add Exynos audio subsystem clock controller node
  clk: samsung: register audio subsystem clocks using common clock framework
  ARM: dts: use #include for all device trees for Samsung

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2013-06-20 22:27:52 +02:00
commit 0c6abd1f25
28 changed files with 288 additions and 56 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

64
Documentation/devicetree/bindings/clock/clk-exynos-audss.txt Normal file
View File

@ -0,0 +1,64 @@
* Samsung Audio Subsystem Clock Controller
The Samsung Audio Subsystem clock controller generates and supplies clocks
to Audio Subsystem block available in the S5PV210 and Exynos SoCs. The clock
binding described here is applicable to all SoC's in Exynos family.
Required Properties:
- compatible: should be one of the following:
- "samsung,exynos4210-audss-clock" - controller compatible with all Exynos4 SoCs.
- "samsung,exynos5250-audss-clock" - controller compatible with all Exynos5 SoCs.
- reg: physical base address and length of the controller's register set.
- #clock-cells: should be 1.
The following is the list of clocks generated by the controller. Each clock is
assigned an identifier and client nodes use this identifier to specify the
clock which they consume. Some of the clocks are available only on a particular
Exynos4 SoC and this is specified where applicable.
Provided clocks:
Clock ID SoC (if specific)
-----------------------------------------------
mout_audss 0
mout_i2s 1
dout_srp 2
dout_aud_bus 3
dout_i2s 4
srp_clk 5
i2s_bus 6
sclk_i2s 7
pcm_bus 8
sclk_pcm 9
Example 1: An example of a clock controller node is listed below.
clock_audss: audss-clock-controller@3810000 {
compatible = "samsung,exynos5250-audss-clock";
reg = <0x03810000 0x0C>;
#clock-cells = <1>;
};
Example 2: I2S controller node that consumes the clock generated by the clock
controller. Refer to the standard clock bindings for information
about 'clocks' and 'clock-names' property.
i2s0: i2s@03830000 {
compatible = "samsung,i2s-v5";
reg = <0x03830000 0x100>;
dmas = <&pdma0 10
&pdma0 9
&pdma0 8>;
dma-names = "tx", "rx", "tx-sec";
clocks = <&clock_audss EXYNOS_I2S_BUS>,
<&clock_audss EXYNOS_I2S_BUS>,
<&clock_audss EXYNOS_SCLK_I2S>,
<&clock_audss EXYNOS_MOUT_AUDSS>,
<&clock_audss EXYNOS_MOUT_I2S>;
clock-names = "iis", "i2s_opclk0", "i2s_opclk1",
"mout_audss", "mout_i2s";
};

46
Documentation/devicetree/bindings/sound/samsung-i2s.txt
View File

@ -8,6 +8,16 @@ Required SoC Specific Properties:
- dmas: list of DMA controller phandle and DMA request line ordered pairs.
- dma-names: identifier string for each DMA request line in the dmas property.
These strings correspond 1:1 with the ordered pairs in dmas.
- clocks: Handle to iis clock and RCLK source clk.
- clock-names:
i2s0 uses some base clks from CMU and some are from audio subsystem internal
clock controller. The clock names for i2s0 should be "iis", "i2s_opclk0" and
"i2s_opclk1" as shown in the example below.
i2s1 and i2s2 uses clocks from CMU. The clock names for i2s1 and i2s2 should
be "iis" and "i2s_opclk0".
"iis" is the i2s bus clock and i2s_opclk0, i2s_opclk1 are sources of the root
clk. i2s0 has internal mux to select the source of root clk and i2s1 and i2s2
doesn't have any such mux.
Optional SoC Specific Properties:
@ -20,44 +30,26 @@ Optional SoC Specific Properties:
then this flag is enabled.
- samsung,idma-addr: Internal DMA register base address of the audio
sub system(used in secondary sound source).
Required Board Specific Properties:
- gpios: The gpio specifier for data out,data in, LRCLK, CDCLK and SCLK
interface lines. The format of the gpio specifier depends on the gpio
controller.
The syntax of samsung gpio specifier is
<[phandle of the gpio controller node]
[pin number within the gpio controller]
[mux function]
[flags and pull up/down]
[drive strength]>
- pinctrl-0: Should specify pin control groups used for this controller.
- pinctrl-names: Should contain only one value - "default".
Example:
- SoC Specific Portion:
i2s@03830000 {
i2s0: i2s@03830000 {
compatible = "samsung,i2s-v5";
reg = <0x03830000 0x100>;
dmas = <&pdma0 10
&pdma0 9
&pdma0 8>;
dma-names = "tx", "rx", "tx-sec";
clocks = <&clock_audss EXYNOS_I2S_BUS>,
<&clock_audss EXYNOS_I2S_BUS>,
<&clock_audss EXYNOS_SCLK_I2S>;
clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
samsung,supports-6ch;
samsung,supports-rstclr;
samsung,supports-secdai;
samsung,idma-addr = <0x03000000>;
};
- Board Specific Portion:
i2s@03830000 {
gpios = <&gpz 0 2 0 0>, /* I2S_0_SCLK */
<&gpz 1 2 0 0>, /* I2S_0_CDCLK */
<&gpz 2 2 0 0>, /* I2S_0_LRCK */
<&gpz 3 2 0 0>, /* I2S_0_SDI */
<&gpz 4 2 0 0>, /* I2S_0_SDO[1] */
<&gpz 5 2 0 0>, /* I2S_0_SDO[2] */
<&gpz 6 2 0 0>; /* I2S_0_SDO[3] */
pinctrl-names = "default";
pinctrl-0 = <&i2s0_bus>;
};

2
arch/arm/boot/dts/exynos4.dtsi
View File

@ -19,7 +19,7 @@
* published by the Free Software Foundation.
*/
/include/ "skeleton.dtsi"
#include "skeleton.dtsi"
/ {
interrupt-parent = <&gic>;

2
arch/arm/boot/dts/exynos4210-origen.dts
View File

@ -15,7 +15,7 @@
*/
/dts-v1/;
/include/ "exynos4210.dtsi"
#include "exynos4210.dtsi"
/ {
model = "Insignal Origen evaluation board based on Exynos4210";

2
arch/arm/boot/dts/exynos4210-smdkv310.dts
View File

@ -15,7 +15,7 @@
*/
/dts-v1/;
/include/ "exynos4210.dtsi"
#include "exynos4210.dtsi"
/ {
model = "Samsung smdkv310 evaluation board based on Exynos4210";

2
arch/arm/boot/dts/exynos4210-trats.dts
View File

@ -13,7 +13,7 @@
*/
/dts-v1/;
/include/ "exynos4210.dtsi"
#include "exynos4210.dtsi"
/ {
model = "Samsung Trats based on Exynos4210";

2
arch/arm/boot/dts/exynos4210-universal_c210.dts
View File

@ -13,7 +13,7 @@
*/
/dts-v1/;
/include/ "exynos4210.dtsi"
#include "exynos4210.dtsi"
/ {
model = "Samsung Universal C210 based on Exynos4210 rev0";

4
arch/arm/boot/dts/exynos4210.dtsi
View File

@ -19,8 +19,8 @@
* published by the Free Software Foundation.
*/
/include/ "exynos4.dtsi"
/include/ "exynos4210-pinctrl.dtsi"
#include "exynos4.dtsi"
#include "exynos4210-pinctrl.dtsi"
/ {
compatible = "samsung,exynos4210";

2
arch/arm/boot/dts/exynos4212.dtsi
View File

@ -17,7 +17,7 @@
* published by the Free Software Foundation.
*/
/include/ "exynos4x12.dtsi"
#include "exynos4x12.dtsi"
/ {
compatible = "samsung,exynos4212";

2
arch/arm/boot/dts/exynos4412-odroidx.dts
View File

@ -12,7 +12,7 @@
*/
/dts-v1/;
/include/ "exynos4412.dtsi"
#include "exynos4412.dtsi"
/ {
model = "Hardkernel ODROID-X board based on Exynos4412";

2
arch/arm/boot/dts/exynos4412-origen.dts
View File

@ -13,7 +13,7 @@
*/
/dts-v1/;
/include/ "exynos4412.dtsi"
#include "exynos4412.dtsi"
/ {
model = "Insignal Origen evaluation board based on Exynos4412";

2
arch/arm/boot/dts/exynos4412-smdk4412.dts
View File

@ -13,7 +13,7 @@
*/
/dts-v1/;
/include/ "exynos4412.dtsi"
#include "exynos4412.dtsi"
/ {
model = "Samsung SMDK evaluation board based on Exynos4412";

2
arch/arm/boot/dts/exynos4412.dtsi
View File

@ -17,7 +17,7 @@
* published by the Free Software Foundation.
*/
/include/ "exynos4x12.dtsi"
#include "exynos4x12.dtsi"
/ {
compatible = "samsung,exynos4412";

4
arch/arm/boot/dts/exynos4x12.dtsi
View File

@ -17,8 +17,8 @@
* published by the Free Software Foundation.
*/
/include/ "exynos4.dtsi"
/include/ "exynos4x12-pinctrl.dtsi"
#include "exynos4.dtsi"
#include "exynos4x12-pinctrl.dtsi"
/ {
aliases {

2
arch/arm/boot/dts/exynos5250-arndale.dts
View File

@ -10,7 +10,7 @@
*/
/dts-v1/;
/include/ "exynos5250.dtsi"
#include "exynos5250.dtsi"
/ {
model = "Insignal Arndale evaluation board based on EXYNOS5250";

2
arch/arm/boot/dts/exynos5250-smdk5250.dts
View File

@ -10,7 +10,7 @@
*/
/dts-v1/;
/include/ "exynos5250.dtsi"
#include "exynos5250.dtsi"
/ {
model = "SAMSUNG SMDK5250 board based on EXYNOS5250";

4
arch/arm/boot/dts/exynos5250-snow.dts
View File

@ -9,8 +9,8 @@
*/
/dts-v1/;
/include/ "exynos5250.dtsi"
/include/ "cros5250-common.dtsi"
#include "exynos5250.dtsi"
#include "cros5250-common.dtsi"
/ {
model = "Google Snow";

20
arch/arm/boot/dts/exynos5250.dtsi
View File

@ -17,8 +17,10 @@
* published by the Free Software Foundation.
*/
/include/ "skeleton.dtsi"
/include/ "exynos5250-pinctrl.dtsi"
#include "skeleton.dtsi"
#include "exynos5250-pinctrl.dtsi"
#include <dt-bindings/clk/exynos-audss-clk.h>
/ {
compatible = "samsung,exynos5250";
@ -72,6 +74,12 @@
#clock-cells = <1>;
};
clock_audss: audss-clock-controller@3810000 {
compatible = "samsung,exynos5250-audss-clock";
reg = <0x03810000 0x0C>;
#clock-cells = <1>;
};
gic:interrupt-controller@10481000 {
compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
#interrupt-cells = <3>;
@ -451,6 +459,10 @@
&pdma0 9
&pdma0 8>;
dma-names = "tx", "rx", "tx-sec";
clocks = <&clock_audss EXYNOS_I2S_BUS>,
<&clock_audss EXYNOS_I2S_BUS>,
<&clock_audss EXYNOS_SCLK_I2S>;
clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
samsung,supports-6ch;
samsung,supports-rstclr;
samsung,supports-secdai;
@ -465,6 +477,8 @@
dmas = <&pdma1 12
&pdma1 11>;
dma-names = "tx", "rx";
clocks = <&clock 307>, <&clock 157>;
clock-names = "iis", "i2s_opclk0";
pinctrl-names = "default";
pinctrl-0 = <&i2s1_bus>;
};
@ -475,6 +489,8 @@
dmas = <&pdma0 12
&pdma0 11>;
dma-names = "tx", "rx";
clocks = <&clock 308>, <&clock 158>;
clock-names = "iis", "i2s_opclk0";
pinctrl-names = "default";
pinctrl-0 = <&i2s2_bus>;
};

2
arch/arm/boot/dts/exynos5440-sd5v1.dts
View File

@ -10,7 +10,7 @@
*/
/dts-v1/;
/include/ "exynos5440.dtsi"
#include "exynos5440.dtsi"
/ {
model = "SAMSUNG SD5v1 board based on EXYNOS5440";

2
arch/arm/boot/dts/exynos5440-ssdk5440.dts
View File

@ -10,7 +10,7 @@
*/
/dts-v1/;
/include/ "exynos5440.dtsi"
#include "exynos5440.dtsi"
/ {
model = "SAMSUNG SSDK5440 board based on EXYNOS5440";

2
arch/arm/boot/dts/exynos5440.dtsi
View File

@ -9,7 +9,7 @@
* published by the Free Software Foundation.
*/
/include/ "skeleton.dtsi"
#include "skeleton.dtsi"
/ {
compatible = "samsung,exynos5440";

2
arch/arm/boot/dts/s3c2416-smdk2416.dts
View File

@ -9,7 +9,7 @@
*/
/dts-v1/;
/include/ "s3c2416.dtsi"
#include "s3c2416.dtsi"
/ {
model = "SMDK2416";

4
arch/arm/boot/dts/s3c2416.dtsi
View File

@ -8,8 +8,8 @@
* published by the Free Software Foundation.
*/
/include/ "s3c24xx.dtsi"
/include/ "s3c2416-pinctrl.dtsi"
#include "s3c24xx.dtsi"
#include "s3c2416-pinctrl.dtsi"
/ {
model = "Samsung S3C2416 SoC";

2
arch/arm/boot/dts/s3c24xx.dtsi
View File

@ -8,7 +8,7 @@
* published by the Free Software Foundation.
*/
/include/ "skeleton.dtsi"
#include "skeleton.dtsi"
/ {
compatible = "samsung,s3c24xx";

1
drivers/clk/samsung/Makefile
View File

@ -6,3 +6,4 @@ obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o
obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o
obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o
obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o
obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o

133
drivers/clk/samsung/clk-exynos-audss.c Normal file
View File

@ -0,0 +1,133 @@
/*
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
* Author: Padmavathi Venna <padma.v@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Common Clock Framework support for Audio Subsystem Clock Controller.
*/
#include <linux/clkdev.h>
#include <linux/io.h>
#include <linux/clk-provider.h>
#include <linux/of_address.h>
#include <linux/syscore_ops.h>
#include <dt-bindings/clk/exynos-audss-clk.h>
static DEFINE_SPINLOCK(lock);
static struct clk **clk_table;
static void __iomem *reg_base;
static struct clk_onecell_data clk_data;
#define ASS_CLK_SRC 0x0
#define ASS_CLK_DIV 0x4
#define ASS_CLK_GATE 0x8
static unsigned long reg_save[][2] = {
{ASS_CLK_SRC, 0},
{ASS_CLK_DIV, 0},
{ASS_CLK_GATE, 0},
};
/* list of all parent clock list */
static const char *mout_audss_p[] = { "fin_pll", "fout_epll" };
static const char *mout_i2s_p[] = { "mout_audss", "cdclk0", "sclk_audio0" };
#ifdef CONFIG_PM_SLEEP
static int exynos_audss_clk_suspend(void)
{
int i;
for (i = 0; i < ARRAY_SIZE(reg_save); i++)
reg_save[i][1] = readl(reg_base + reg_save[i][0]);
return 0;
}
static void exynos_audss_clk_resume(void)
{
int i;
for (i = 0; i < ARRAY_SIZE(reg_save); i++)
writel(reg_save[i][1], reg_base + reg_save[i][0]);
}
static struct syscore_ops exynos_audss_clk_syscore_ops = {
.suspend = exynos_audss_clk_suspend,
.resume = exynos_audss_clk_resume,
};
#endif /* CONFIG_PM_SLEEP */
/* register exynos_audss clocks */
void __init exynos_audss_clk_init(struct device_node *np)
{
reg_base = of_iomap(np, 0);
if (!reg_base) {
pr_err("%s: failed to map audss registers\n", __func__);
return;
}
clk_table = kzalloc(sizeof(struct clk *) * EXYNOS_AUDSS_MAX_CLKS,
GFP_KERNEL);
if (!clk_table) {
pr_err("%s: could not allocate clk lookup table\n", __func__);
return;
}
clk_data.clks = clk_table;
clk_data.clk_num = EXYNOS_AUDSS_MAX_CLKS;
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
clk_table[EXYNOS_MOUT_AUDSS] = clk_register_mux(NULL, "mout_audss",
mout_audss_p, ARRAY_SIZE(mout_audss_p), 0,
reg_base + ASS_CLK_SRC, 0, 1, 0, &lock);
clk_table[EXYNOS_MOUT_I2S] = clk_register_mux(NULL, "mout_i2s",
mout_i2s_p, ARRAY_SIZE(mout_i2s_p), 0,
reg_base + ASS_CLK_SRC, 2, 2, 0, &lock);
clk_table[EXYNOS_DOUT_SRP] = clk_register_divider(NULL, "dout_srp",
"mout_audss", 0, reg_base + ASS_CLK_DIV, 0, 4,
0, &lock);
clk_table[EXYNOS_DOUT_AUD_BUS] = clk_register_divider(NULL,
"dout_aud_bus", "dout_srp", 0,
reg_base + ASS_CLK_DIV, 4, 4, 0, &lock);
clk_table[EXYNOS_DOUT_I2S] = clk_register_divider(NULL, "dout_i2s",
"mout_i2s", 0, reg_base + ASS_CLK_DIV, 8, 4, 0,
&lock);
clk_table[EXYNOS_SRP_CLK] = clk_register_gate(NULL, "srp_clk",
"dout_srp", CLK_SET_RATE_PARENT,
reg_base + ASS_CLK_GATE, 0, 0, &lock);
clk_table[EXYNOS_I2S_BUS] = clk_register_gate(NULL, "i2s_bus",
"dout_aud_bus", CLK_SET_RATE_PARENT,
reg_base + ASS_CLK_GATE, 2, 0, &lock);
clk_table[EXYNOS_SCLK_I2S] = clk_register_gate(NULL, "sclk_i2s",
"dout_i2s", CLK_SET_RATE_PARENT,
reg_base + ASS_CLK_GATE, 3, 0, &lock);
clk_table[EXYNOS_PCM_BUS] = clk_register_gate(NULL, "pcm_bus",
"sclk_pcm", CLK_SET_RATE_PARENT,
reg_base + ASS_CLK_GATE, 4, 0, &lock);
clk_table[EXYNOS_SCLK_PCM] = clk_register_gate(NULL, "sclk_pcm",
"div_pcm0", CLK_SET_RATE_PARENT,
reg_base + ASS_CLK_GATE, 5, 0, &lock);
#ifdef CONFIG_PM_SLEEP
register_syscore_ops(&exynos_audss_clk_syscore_ops);
#endif
pr_info("Exynos: Audss: clock setup completed\n");
}
CLK_OF_DECLARE(exynos4210_audss_clk, "samsung,exynos4210-audss-clock",
exynos_audss_clk_init);
CLK_OF_DECLARE(exynos5250_audss_clk, "samsung,exynos5250-audss-clock",
exynos_audss_clk_init);

5
drivers/clk/samsung/clk-exynos5250.c
View File

@ -87,6 +87,7 @@ enum exynos5250_clks {
sclk_mmc0, sclk_mmc1, sclk_mmc2, sclk_mmc3, sclk_sata, sclk_usb3,
sclk_jpeg, sclk_uart0, sclk_uart1, sclk_uart2, sclk_uart3, sclk_pwm,
sclk_audio1, sclk_audio2, sclk_spdif, sclk_spi0, sclk_spi1, sclk_spi2,
div_i2s1, div_i2s2,
/* gate clocks */
gscl0 = 256, gscl1, gscl2, gscl3, gscl_wa, gscl_wb, smmu_gscl0,
@ -291,8 +292,8 @@ struct samsung_div_clock exynos5250_div_clks[] __initdata = {
DIV(none, "div_pcm1", "sclk_audio1", DIV_PERIC4, 4, 8),
DIV(none, "div_audio2", "mout_audio2", DIV_PERIC4, 16, 4),
DIV(none, "div_pcm2", "sclk_audio2", DIV_PERIC4, 20, 8),
DIV(none, "div_i2s1", "sclk_audio1", DIV_PERIC5, 0, 6),
DIV(none, "div_i2s2", "sclk_audio2", DIV_PERIC5, 8, 6),
DIV(div_i2s1, "div_i2s1", "sclk_audio1", DIV_PERIC5, 0, 6),
DIV(div_i2s2, "div_i2s2", "sclk_audio2", DIV_PERIC5, 8, 6),
DIV(sclk_pixel, "div_hdmi_pixel", "sclk_vpll", DIV_DISP1_0, 28, 4),
DIV_A(none, "armclk", "div_arm", DIV_CPU0, 28, 3, "armclk"),
DIV_F(none, "div_mipi1_pre", "div_mipi1",

25
include/dt-bindings/clk/exynos-audss-clk.h Normal file
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/*
* This header provides constants for Samsung audio subsystem
* clock controller.
*
* The constants defined in this header are being used in dts
* and exynos audss driver.
*/
#ifndef _DT_BINDINGS_CLK_EXYNOS_AUDSS_H
#define _DT_BINDINGS_CLK_EXYNOS_AUDSS_H
#define EXYNOS_MOUT_AUDSS 0
#define EXYNOS_MOUT_I2S 1
#define EXYNOS_DOUT_SRP 2
#define EXYNOS_DOUT_AUD_BUS 3
#define EXYNOS_DOUT_I2S 4
#define EXYNOS_SRP_CLK 5
#define EXYNOS_I2S_BUS 6
#define EXYNOS_SCLK_I2S 7
#define EXYNOS_PCM_BUS 8
#define EXYNOS_SCLK_PCM 9
#define EXYNOS_AUDSS_MAX_CLKS 10
#endif