forked from Minki/linux
drm/amd/display: Refactor stream encoder for HW review
Move DCN1 implementation of stream encoder to new file (instead of common dce_stream_encoder.c). Cleanup code related to different implementation due to register definition differences. Signed-off-by: Eric Bernstein <eric.bernstein@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Eric Bernstein
Alex Deucher
parent
1402c60517
commit
0c41891c81
@ -26,7 +26,7 @@ DCN10 = dcn10_resource.o dcn10_ipp.o dcn10_hw_sequencer.o \
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dcn10_dpp.o dcn10_opp.o dcn10_optc.o \
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dcn10_hubp.o dcn10_mpc.o \
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dcn10_dpp_dscl.o dcn10_dpp_cm.o dcn10_cm_common.o \
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dcn10_hubbub.o
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dcn10_hubbub.o dcn10_stream_encoder.o
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AMD_DAL_DCN10 = $(addprefix $(AMDDALPATH)/dc/dcn10/,$(DCN10))
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@ -39,7 +39,7 @@
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#include "dce110/dce110_hw_sequencer.h"
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#include "dcn10/dcn10_opp.h"
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#include "dce/dce_link_encoder.h"
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#include "dce/dce_stream_encoder.h"
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#include "dcn10/dcn10_stream_encoder.h"
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#include "dce/dce_clocks.h"
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#include "dce/dce_clock_source.h"
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#include "dce/dce_audio.h"
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@ -166,36 +166,22 @@ static const struct dce_abm_mask abm_mask = {
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#define stream_enc_regs(id)\
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[id] = {\
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SE_DCN_REG_LIST(id),\
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.TMDS_CNTL = 0,\
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.AFMT_AVI_INFO0 = 0,\
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.AFMT_AVI_INFO1 = 0,\
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.AFMT_AVI_INFO2 = 0,\
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.AFMT_AVI_INFO3 = 0,\
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SE_DCN_REG_LIST(id)\
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}
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static const struct dce110_stream_enc_registers stream_enc_regs[] = {
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static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
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stream_enc_regs(0),
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stream_enc_regs(1),
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stream_enc_regs(2),
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stream_enc_regs(3),
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};
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static const struct dce_stream_encoder_shift se_shift = {
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static const struct dcn10_stream_encoder_shift se_shift = {
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SE_COMMON_MASK_SH_LIST_DCN10(__SHIFT)
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};
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static const struct dce_stream_encoder_mask se_mask = {
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SE_COMMON_MASK_SH_LIST_DCN10(_MASK),
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.AFMT_GENERIC0_UPDATE = 0,
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.AFMT_GENERIC2_UPDATE = 0,
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.DP_DYN_RANGE = 0,
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.DP_YCBCR_RANGE = 0,
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.HDMI_AVI_INFO_SEND = 0,
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.HDMI_AVI_INFO_CONT = 0,
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.HDMI_AVI_INFO_LINE = 0,
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.DP_SEC_AVI_ENABLE = 0,
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.AFMT_AVI_INFO_VERSION = 0
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static const struct dcn10_stream_encoder_mask se_mask = {
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SE_COMMON_MASK_SH_LIST_DCN10(_MASK)
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};
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#define audio_regs(id)\
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@ -653,16 +639,16 @@ static struct stream_encoder *dcn10_stream_encoder_create(
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enum engine_id eng_id,
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struct dc_context *ctx)
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{
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struct dce110_stream_encoder *enc110 =
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kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL);
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struct dcn10_stream_encoder *enc1 =
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kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
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if (!enc110)
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if (!enc1)
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return NULL;
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dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id,
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dcn10_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id,
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&stream_enc_regs[eng_id],
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&se_shift, &se_mask);
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return &enc110->base;
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return &enc1->base;
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}
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static const struct dce_hwseq_registers hwseq_reg = {
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1505
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
Normal file
1505
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
Normal file
File diff suppressed because it is too large
Load Diff
584
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
Normal file
584
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
Normal file
@ -0,0 +1,584 @@
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/*
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* Copyright 2012-15 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#ifndef __DC_STREAM_ENCODER_DCN10_H__
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#define __DC_STREAM_ENCODER_DCN10_H__
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#include "stream_encoder.h"
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#define DCN10STRENC_FROM_STRENC(stream_encoder)\
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container_of(stream_encoder, struct dcn10_stream_encoder, base)
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#define SE_COMMON_REG_LIST_BASE(id) \
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SRI(AFMT_GENERIC_0, DIG, id), \
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SRI(AFMT_GENERIC_1, DIG, id), \
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SRI(AFMT_GENERIC_2, DIG, id), \
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SRI(AFMT_GENERIC_3, DIG, id), \
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SRI(AFMT_GENERIC_4, DIG, id), \
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SRI(AFMT_GENERIC_5, DIG, id), \
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SRI(AFMT_GENERIC_6, DIG, id), \
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SRI(AFMT_GENERIC_7, DIG, id), \
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SRI(AFMT_GENERIC_HDR, DIG, id), \
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SRI(AFMT_INFOFRAME_CONTROL0, DIG, id), \
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SRI(AFMT_VBI_PACKET_CONTROL, DIG, id), \
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SRI(AFMT_AUDIO_PACKET_CONTROL, DIG, id), \
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SRI(AFMT_AUDIO_PACKET_CONTROL2, DIG, id), \
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SRI(AFMT_AUDIO_SRC_CONTROL, DIG, id), \
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SRI(AFMT_60958_0, DIG, id), \
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SRI(AFMT_60958_1, DIG, id), \
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SRI(AFMT_60958_2, DIG, id), \
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SRI(DIG_FE_CNTL, DIG, id), \
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SRI(HDMI_CONTROL, DIG, id), \
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SRI(HDMI_GC, DIG, id), \
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SRI(HDMI_GENERIC_PACKET_CONTROL0, DIG, id), \
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SRI(HDMI_GENERIC_PACKET_CONTROL1, DIG, id), \
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SRI(HDMI_INFOFRAME_CONTROL0, DIG, id), \
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SRI(HDMI_INFOFRAME_CONTROL1, DIG, id), \
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SRI(HDMI_VBI_PACKET_CONTROL, DIG, id), \
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SRI(HDMI_AUDIO_PACKET_CONTROL, DIG, id),\
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SRI(HDMI_ACR_PACKET_CONTROL, DIG, id),\
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SRI(HDMI_ACR_32_0, DIG, id),\
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SRI(HDMI_ACR_32_1, DIG, id),\
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SRI(HDMI_ACR_44_0, DIG, id),\
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SRI(HDMI_ACR_44_1, DIG, id),\
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SRI(HDMI_ACR_48_0, DIG, id),\
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SRI(HDMI_ACR_48_1, DIG, id),\
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SRI(TMDS_CNTL, DIG, id), \
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SRI(DP_MSE_RATE_CNTL, DP, id), \
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SRI(DP_MSE_RATE_UPDATE, DP, id), \
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SRI(DP_PIXEL_FORMAT, DP, id), \
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SRI(DP_SEC_CNTL, DP, id), \
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SRI(DP_STEER_FIFO, DP, id), \
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SRI(DP_VID_M, DP, id), \
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SRI(DP_VID_N, DP, id), \
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SRI(DP_VID_STREAM_CNTL, DP, id), \
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SRI(DP_VID_TIMING, DP, id), \
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SRI(DP_SEC_AUD_N, DP, id), \
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SRI(DP_SEC_TIMESTAMP, DP, id)
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#define SE_DCN_REG_LIST(id)\
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SE_COMMON_REG_LIST_BASE(id),\
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SRI(AFMT_CNTL, DIG, id),\
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SRI(AFMT_VBI_PACKET_CONTROL1, DIG, id),\
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SRI(HDMI_GENERIC_PACKET_CONTROL2, DIG, id), \
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SRI(HDMI_GENERIC_PACKET_CONTROL3, DIG, id), \
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SRI(DP_DB_CNTL, DP, id), \
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SRI(DP_MSA_MISC, DP, id), \
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SRI(DP_MSA_COLORIMETRY, DP, id), \
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SRI(DP_MSA_TIMING_PARAM1, DP, id), \
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SRI(DP_MSA_TIMING_PARAM2, DP, id), \
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SRI(DP_MSA_TIMING_PARAM3, DP, id), \
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SRI(DP_MSA_TIMING_PARAM4, DP, id), \
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SRI(HDMI_DB_CONTROL, DIG, id)
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#define SE_SF(reg_name, field_name, post_fix)\
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.field_name = reg_name ## __ ## field_name ## post_fix
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#define SE_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh)\
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SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_INDEX, mask_sh),\
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SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB0, mask_sh),\
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SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB1, mask_sh),\
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SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB2, mask_sh),\
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SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB3, mask_sh),\
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SE_SF(DP0_DP_PIXEL_FORMAT, DP_PIXEL_ENCODING, mask_sh),\
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SE_SF(DP0_DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH, mask_sh),\
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SE_SF(DIG0_HDMI_CONTROL, HDMI_PACKET_GEN_VERSION, mask_sh),\
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SE_SF(DIG0_HDMI_CONTROL, HDMI_KEEPOUT_MODE, mask_sh),\
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SE_SF(DIG0_HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, mask_sh),\
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SE_SF(DIG0_HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, mask_sh),\
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SE_SF(DIG0_HDMI_CONTROL, HDMI_DATA_SCRAMBLE_EN, mask_sh),\
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SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, mask_sh),\
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SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, mask_sh),\
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SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, mask_sh),\
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SE_SF(DIG0_HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, mask_sh),\
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SE_SF(DIG0_AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, mask_sh),\
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SE_SF(DIG0_HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, mask_sh),\
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SE_SF(DIG0_HDMI_GC, HDMI_GC_AVMUTE, mask_sh),\
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SE_SF(DP0_DP_MSE_RATE_CNTL, DP_MSE_RATE_X, mask_sh),\
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SE_SF(DP0_DP_MSE_RATE_CNTL, DP_MSE_RATE_Y, mask_sh),\
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SE_SF(DP0_DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING, mask_sh),\
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SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, mask_sh),\
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SE_SF(DP0_DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, mask_sh),\
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SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP1_ENABLE, mask_sh),\
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SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, mask_sh),\
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SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, mask_sh),\
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SE_SF(DP0_DP_SEC_CNTL, DP_SEC_MPG_ENABLE, mask_sh),\
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SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, mask_sh),\
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SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, mask_sh),\
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SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, mask_sh),\
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SE_SF(DP0_DP_STEER_FIFO, DP_STEER_FIFO_RESET, mask_sh),\
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SE_SF(DP0_DP_VID_TIMING, DP_VID_M_N_GEN_EN, mask_sh),\
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SE_SF(DP0_DP_VID_N, DP_VID_N, mask_sh),\
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SE_SF(DP0_DP_VID_M, DP_VID_M, mask_sh),\
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SE_SF(DIG0_DIG_FE_CNTL, DIG_START, mask_sh),\
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SE_SF(DIG0_AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, mask_sh),\
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SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, mask_sh),\
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SE_SF(DIG0_HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, mask_sh),\
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SE_SF(DIG0_HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, mask_sh),\
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SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, mask_sh),\
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SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_LAYOUT_OVRD, mask_sh),\
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SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL2, AFMT_60958_OSF_OVRD, mask_sh),\
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SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, mask_sh),\
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SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, mask_sh),\
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SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUDIO_PRIORITY, mask_sh),\
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SE_SF(DIG0_HDMI_ACR_32_0, HDMI_ACR_CTS_32, mask_sh),\
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SE_SF(DIG0_HDMI_ACR_32_1, HDMI_ACR_N_32, mask_sh),\
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SE_SF(DIG0_HDMI_ACR_44_0, HDMI_ACR_CTS_44, mask_sh),\
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SE_SF(DIG0_HDMI_ACR_44_1, HDMI_ACR_N_44, mask_sh),\
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SE_SF(DIG0_HDMI_ACR_48_0, HDMI_ACR_CTS_48, mask_sh),\
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SE_SF(DIG0_HDMI_ACR_48_1, HDMI_ACR_N_48, mask_sh),\
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SE_SF(DIG0_AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, mask_sh),\
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SE_SF(DIG0_AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, mask_sh),\
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SE_SF(DIG0_AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, mask_sh),\
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SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, mask_sh),\
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SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, mask_sh),\
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SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, mask_sh),\
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SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, mask_sh),\
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SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, mask_sh),\
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SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, mask_sh),\
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SE_SF(DP0_DP_SEC_AUD_N, DP_SEC_AUD_N, mask_sh),\
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SE_SF(DP0_DP_SEC_TIMESTAMP, DP_SEC_TIMESTAMP_MODE, mask_sh),\
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SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ASP_ENABLE, mask_sh),\
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SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ATP_ENABLE, mask_sh),\
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SE_SF(DP0_DP_SEC_CNTL, DP_SEC_AIP_ENABLE, mask_sh),\
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SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ACM_ENABLE, mask_sh),\
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SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, mask_sh),\
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SE_SF(DIG0_AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, mask_sh),\
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SE_SF(DIG0_HDMI_CONTROL, HDMI_CLOCK_CHANNEL_RATE, mask_sh),\
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SE_SF(DIG0_DIG_FE_CNTL, TMDS_PIXEL_ENCODING, mask_sh),\
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SE_SF(DIG0_DIG_FE_CNTL, TMDS_COLOR_FORMAT, mask_sh),\
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SE_SF(DIG0_DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, mask_sh),\
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SE_SF(DIG0_DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, mask_sh),\
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SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_LOCK_STATUS, mask_sh),\
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SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT, mask_sh),\
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SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, mask_sh),\
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SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC0_FRAME_UPDATE_PENDING, mask_sh),\
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SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC1_FRAME_UPDATE_PENDING, mask_sh),\
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SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC2_FRAME_UPDATE_PENDING, mask_sh),\
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SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC3_FRAME_UPDATE_PENDING, mask_sh),\
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SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_FRAME_UPDATE_PENDING, mask_sh),\
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SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC5_FRAME_UPDATE_PENDING, mask_sh),\
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SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC6_FRAME_UPDATE_PENDING, mask_sh),\
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SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC7_FRAME_UPDATE_PENDING, mask_sh),\
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SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC0_FRAME_UPDATE, mask_sh),\
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SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC1_FRAME_UPDATE, mask_sh),\
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SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC2_FRAME_UPDATE, mask_sh),\
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SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC3_FRAME_UPDATE, mask_sh),\
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SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_FRAME_UPDATE, mask_sh),\
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SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC5_FRAME_UPDATE, mask_sh),\
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SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC6_FRAME_UPDATE, mask_sh),\
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SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC7_FRAME_UPDATE, mask_sh),\
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SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP4_ENABLE, mask_sh),\
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SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP5_ENABLE, mask_sh),\
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SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP6_ENABLE, mask_sh),\
|
||||
SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP7_ENABLE, mask_sh),\
|
||||
SE_SF(DP0_DP_DB_CNTL, DP_DB_DISABLE, mask_sh),\
|
||||
SE_SF(DP0_DP_MSA_COLORIMETRY, DP_MSA_MISC0, mask_sh),\
|
||||
SE_SF(DP0_DP_MSA_TIMING_PARAM1, DP_MSA_HTOTAL, mask_sh),\
|
||||
SE_SF(DP0_DP_MSA_TIMING_PARAM1, DP_MSA_VTOTAL, mask_sh),\
|
||||
SE_SF(DP0_DP_MSA_TIMING_PARAM2, DP_MSA_HSTART, mask_sh),\
|
||||
SE_SF(DP0_DP_MSA_TIMING_PARAM2, DP_MSA_VSTART, mask_sh),\
|
||||
SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_HSYNCWIDTH, mask_sh),\
|
||||
SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_HSYNCPOLARITY, mask_sh),\
|
||||
SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_VSYNCWIDTH, mask_sh),\
|
||||
SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_VSYNCPOLARITY, mask_sh),\
|
||||
SE_SF(DP0_DP_MSA_TIMING_PARAM4, DP_MSA_HWIDTH, mask_sh),\
|
||||
SE_SF(DP0_DP_MSA_TIMING_PARAM4, DP_MSA_VHEIGHT, mask_sh),\
|
||||
SE_SF(DIG0_HDMI_DB_CONTROL, HDMI_DB_DISABLE, mask_sh),\
|
||||
SE_SF(DP0_DP_VID_TIMING, DP_VID_N_MUL, mask_sh)
|
||||
|
||||
#define SE_COMMON_MASK_SH_LIST_SOC(mask_sh)\
|
||||
SE_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh)
|
||||
|
||||
#define SE_COMMON_MASK_SH_LIST_DCN10(mask_sh)\
|
||||
SE_COMMON_MASK_SH_LIST_SOC(mask_sh),\
|
||||
SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_CONT, mask_sh),\
|
||||
SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_SEND, mask_sh),\
|
||||
SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_LINE, mask_sh),\
|
||||
SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_CONT, mask_sh),\
|
||||
SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_SEND, mask_sh),\
|
||||
SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_LINE, mask_sh)
|
||||
|
||||
struct dcn10_stream_encoder_shift {
|
||||
uint8_t AFMT_GENERIC_INDEX;
|
||||
uint8_t AFMT_GENERIC_HB0;
|
||||
uint8_t AFMT_GENERIC_HB1;
|
||||
uint8_t AFMT_GENERIC_HB2;
|
||||
uint8_t AFMT_GENERIC_HB3;
|
||||
uint8_t AFMT_GENERIC_LOCK_STATUS;
|
||||
uint8_t AFMT_GENERIC_CONFLICT;
|
||||
uint8_t AFMT_GENERIC_CONFLICT_CLR;
|
||||
uint8_t AFMT_GENERIC0_FRAME_UPDATE_PENDING;
|
||||
uint8_t AFMT_GENERIC1_FRAME_UPDATE_PENDING;
|
||||
uint8_t AFMT_GENERIC2_FRAME_UPDATE_PENDING;
|
||||
uint8_t AFMT_GENERIC3_FRAME_UPDATE_PENDING;
|
||||
uint8_t AFMT_GENERIC4_FRAME_UPDATE_PENDING;
|
||||
uint8_t AFMT_GENERIC5_FRAME_UPDATE_PENDING;
|
||||
uint8_t AFMT_GENERIC6_FRAME_UPDATE_PENDING;
|
||||
uint8_t AFMT_GENERIC7_FRAME_UPDATE_PENDING;
|
||||
uint8_t AFMT_GENERIC0_FRAME_UPDATE;
|
||||
uint8_t AFMT_GENERIC1_FRAME_UPDATE;
|
||||
uint8_t AFMT_GENERIC2_FRAME_UPDATE;
|
||||
uint8_t AFMT_GENERIC3_FRAME_UPDATE;
|
||||
uint8_t AFMT_GENERIC4_FRAME_UPDATE;
|
||||
uint8_t AFMT_GENERIC5_FRAME_UPDATE;
|
||||
uint8_t AFMT_GENERIC6_FRAME_UPDATE;
|
||||
uint8_t AFMT_GENERIC7_FRAME_UPDATE;
|
||||
uint8_t HDMI_GENERIC0_CONT;
|
||||
uint8_t HDMI_GENERIC0_SEND;
|
||||
uint8_t HDMI_GENERIC0_LINE;
|
||||
uint8_t HDMI_GENERIC1_CONT;
|
||||
uint8_t HDMI_GENERIC1_SEND;
|
||||
uint8_t HDMI_GENERIC1_LINE;
|
||||
uint8_t HDMI_GENERIC2_CONT;
|
||||
uint8_t HDMI_GENERIC2_SEND;
|
||||
uint8_t HDMI_GENERIC2_LINE;
|
||||
uint8_t HDMI_GENERIC3_CONT;
|
||||
uint8_t HDMI_GENERIC3_SEND;
|
||||
uint8_t HDMI_GENERIC3_LINE;
|
||||
uint8_t HDMI_GENERIC4_CONT;
|
||||
uint8_t HDMI_GENERIC4_SEND;
|
||||
uint8_t HDMI_GENERIC4_LINE;
|
||||
uint8_t HDMI_GENERIC5_CONT;
|
||||
uint8_t HDMI_GENERIC5_SEND;
|
||||
uint8_t HDMI_GENERIC5_LINE;
|
||||
uint8_t HDMI_GENERIC6_CONT;
|
||||
uint8_t HDMI_GENERIC6_SEND;
|
||||
uint8_t HDMI_GENERIC6_LINE;
|
||||
uint8_t HDMI_GENERIC7_CONT;
|
||||
uint8_t HDMI_GENERIC7_SEND;
|
||||
uint8_t HDMI_GENERIC7_LINE;
|
||||
uint8_t DP_PIXEL_ENCODING;
|
||||
uint8_t DP_COMPONENT_DEPTH;
|
||||
uint8_t HDMI_PACKET_GEN_VERSION;
|
||||
uint8_t HDMI_KEEPOUT_MODE;
|
||||
uint8_t HDMI_DEEP_COLOR_ENABLE;
|
||||
uint8_t HDMI_CLOCK_CHANNEL_RATE;
|
||||
uint8_t HDMI_DEEP_COLOR_DEPTH;
|
||||
uint8_t HDMI_GC_CONT;
|
||||
uint8_t HDMI_GC_SEND;
|
||||
uint8_t HDMI_NULL_SEND;
|
||||
uint8_t HDMI_DATA_SCRAMBLE_EN;
|
||||
uint8_t HDMI_AUDIO_INFO_SEND;
|
||||
uint8_t AFMT_AUDIO_INFO_UPDATE;
|
||||
uint8_t HDMI_AUDIO_INFO_LINE;
|
||||
uint8_t HDMI_GC_AVMUTE;
|
||||
uint8_t DP_MSE_RATE_X;
|
||||
uint8_t DP_MSE_RATE_Y;
|
||||
uint8_t DP_MSE_RATE_UPDATE_PENDING;
|
||||
uint8_t DP_SEC_GSP0_ENABLE;
|
||||
uint8_t DP_SEC_STREAM_ENABLE;
|
||||
uint8_t DP_SEC_GSP1_ENABLE;
|
||||
uint8_t DP_SEC_GSP2_ENABLE;
|
||||
uint8_t DP_SEC_GSP3_ENABLE;
|
||||
uint8_t DP_SEC_GSP4_ENABLE;
|
||||
uint8_t DP_SEC_GSP5_ENABLE;
|
||||
uint8_t DP_SEC_GSP6_ENABLE;
|
||||
uint8_t DP_SEC_GSP7_ENABLE;
|
||||
uint8_t DP_SEC_MPG_ENABLE;
|
||||
uint8_t DP_VID_STREAM_DIS_DEFER;
|
||||
uint8_t DP_VID_STREAM_ENABLE;
|
||||
uint8_t DP_VID_STREAM_STATUS;
|
||||
uint8_t DP_STEER_FIFO_RESET;
|
||||
uint8_t DP_VID_M_N_GEN_EN;
|
||||
uint8_t DP_VID_N;
|
||||
uint8_t DP_VID_M;
|
||||
uint8_t DIG_START;
|
||||
uint8_t AFMT_AUDIO_SRC_SELECT;
|
||||
uint8_t AFMT_AUDIO_CHANNEL_ENABLE;
|
||||
uint8_t HDMI_AUDIO_PACKETS_PER_LINE;
|
||||
uint8_t HDMI_AUDIO_DELAY_EN;
|
||||
uint8_t AFMT_60958_CS_UPDATE;
|
||||
uint8_t AFMT_AUDIO_LAYOUT_OVRD;
|
||||
uint8_t AFMT_60958_OSF_OVRD;
|
||||
uint8_t HDMI_ACR_AUTO_SEND;
|
||||
uint8_t HDMI_ACR_SOURCE;
|
||||
uint8_t HDMI_ACR_AUDIO_PRIORITY;
|
||||
uint8_t HDMI_ACR_CTS_32;
|
||||
uint8_t HDMI_ACR_N_32;
|
||||
uint8_t HDMI_ACR_CTS_44;
|
||||
uint8_t HDMI_ACR_N_44;
|
||||
uint8_t HDMI_ACR_CTS_48;
|
||||
uint8_t HDMI_ACR_N_48;
|
||||
uint8_t AFMT_60958_CS_CHANNEL_NUMBER_L;
|
||||
uint8_t AFMT_60958_CS_CLOCK_ACCURACY;
|
||||
uint8_t AFMT_60958_CS_CHANNEL_NUMBER_R;
|
||||
uint8_t AFMT_60958_CS_CHANNEL_NUMBER_2;
|
||||
uint8_t AFMT_60958_CS_CHANNEL_NUMBER_3;
|
||||
uint8_t AFMT_60958_CS_CHANNEL_NUMBER_4;
|
||||
uint8_t AFMT_60958_CS_CHANNEL_NUMBER_5;
|
||||
uint8_t AFMT_60958_CS_CHANNEL_NUMBER_6;
|
||||
uint8_t AFMT_60958_CS_CHANNEL_NUMBER_7;
|
||||
uint8_t DP_SEC_AUD_N;
|
||||
uint8_t DP_SEC_TIMESTAMP_MODE;
|
||||
uint8_t DP_SEC_ASP_ENABLE;
|
||||
uint8_t DP_SEC_ATP_ENABLE;
|
||||
uint8_t DP_SEC_AIP_ENABLE;
|
||||
uint8_t DP_SEC_ACM_ENABLE;
|
||||
uint8_t AFMT_AUDIO_SAMPLE_SEND;
|
||||
uint8_t AFMT_AUDIO_CLOCK_EN;
|
||||
uint8_t TMDS_PIXEL_ENCODING;
|
||||
uint8_t TMDS_COLOR_FORMAT;
|
||||
uint8_t DIG_STEREOSYNC_SELECT;
|
||||
uint8_t DIG_STEREOSYNC_GATE_EN;
|
||||
uint8_t DP_DB_DISABLE;
|
||||
uint8_t DP_MSA_MISC0;
|
||||
uint8_t DP_MSA_HTOTAL;
|
||||
uint8_t DP_MSA_VTOTAL;
|
||||
uint8_t DP_MSA_HSTART;
|
||||
uint8_t DP_MSA_VSTART;
|
||||
uint8_t DP_MSA_HSYNCWIDTH;
|
||||
uint8_t DP_MSA_HSYNCPOLARITY;
|
||||
uint8_t DP_MSA_VSYNCWIDTH;
|
||||
uint8_t DP_MSA_VSYNCPOLARITY;
|
||||
uint8_t DP_MSA_HWIDTH;
|
||||
uint8_t DP_MSA_VHEIGHT;
|
||||
uint8_t HDMI_DB_DISABLE;
|
||||
uint8_t DP_VID_N_MUL;
|
||||
uint8_t DP_VID_M_DOUBLE_VALUE_EN;
|
||||
};
|
||||
|
||||
struct dcn10_stream_encoder_mask {
|
||||
uint32_t AFMT_GENERIC_INDEX;
|
||||
uint32_t AFMT_GENERIC_HB0;
|
||||
uint32_t AFMT_GENERIC_HB1;
|
||||
uint32_t AFMT_GENERIC_HB2;
|
||||
uint32_t AFMT_GENERIC_HB3;
|
||||
uint32_t AFMT_GENERIC_LOCK_STATUS;
|
||||
uint32_t AFMT_GENERIC_CONFLICT;
|
||||
uint32_t AFMT_GENERIC_CONFLICT_CLR;
|
||||
uint32_t AFMT_GENERIC0_FRAME_UPDATE_PENDING;
|
||||
uint32_t AFMT_GENERIC1_FRAME_UPDATE_PENDING;
|
||||
uint32_t AFMT_GENERIC2_FRAME_UPDATE_PENDING;
|
||||
uint32_t AFMT_GENERIC3_FRAME_UPDATE_PENDING;
|
||||
uint32_t AFMT_GENERIC4_FRAME_UPDATE_PENDING;
|
||||
uint32_t AFMT_GENERIC5_FRAME_UPDATE_PENDING;
|
||||
uint32_t AFMT_GENERIC6_FRAME_UPDATE_PENDING;
|
||||
uint32_t AFMT_GENERIC7_FRAME_UPDATE_PENDING;
|
||||
uint32_t AFMT_GENERIC0_FRAME_UPDATE;
|
||||
uint32_t AFMT_GENERIC1_FRAME_UPDATE;
|
||||
uint32_t AFMT_GENERIC2_FRAME_UPDATE;
|
||||
uint32_t AFMT_GENERIC3_FRAME_UPDATE;
|
||||
uint32_t AFMT_GENERIC4_FRAME_UPDATE;
|
||||
uint32_t AFMT_GENERIC5_FRAME_UPDATE;
|
||||
uint32_t AFMT_GENERIC6_FRAME_UPDATE;
|
||||
uint32_t AFMT_GENERIC7_FRAME_UPDATE;
|
||||
uint32_t HDMI_GENERIC0_CONT;
|
||||
uint32_t HDMI_GENERIC0_SEND;
|
||||
uint32_t HDMI_GENERIC0_LINE;
|
||||
uint32_t HDMI_GENERIC1_CONT;
|
||||
uint32_t HDMI_GENERIC1_SEND;
|
||||
uint32_t HDMI_GENERIC1_LINE;
|
||||
uint32_t HDMI_GENERIC2_CONT;
|
||||
uint32_t HDMI_GENERIC2_SEND;
|
||||
uint32_t HDMI_GENERIC2_LINE;
|
||||
uint32_t HDMI_GENERIC3_CONT;
|
||||
uint32_t HDMI_GENERIC3_SEND;
|
||||
uint32_t HDMI_GENERIC3_LINE;
|
||||
uint32_t HDMI_GENERIC4_CONT;
|
||||
uint32_t HDMI_GENERIC4_SEND;
|
||||
uint32_t HDMI_GENERIC4_LINE;
|
||||
uint32_t HDMI_GENERIC5_CONT;
|
||||
uint32_t HDMI_GENERIC5_SEND;
|
||||
uint32_t HDMI_GENERIC5_LINE;
|
||||
uint32_t HDMI_GENERIC6_CONT;
|
||||
uint32_t HDMI_GENERIC6_SEND;
|
||||
uint32_t HDMI_GENERIC6_LINE;
|
||||
uint32_t HDMI_GENERIC7_CONT;
|
||||
uint32_t HDMI_GENERIC7_SEND;
|
||||
uint32_t HDMI_GENERIC7_LINE;
|
||||
uint32_t DP_PIXEL_ENCODING;
|
||||
uint32_t DP_COMPONENT_DEPTH;
|
||||
uint32_t HDMI_PACKET_GEN_VERSION;
|
||||
uint32_t HDMI_KEEPOUT_MODE;
|
||||
uint32_t HDMI_DEEP_COLOR_ENABLE;
|
||||
uint32_t HDMI_CLOCK_CHANNEL_RATE;
|
||||
uint32_t HDMI_DEEP_COLOR_DEPTH;
|
||||
uint32_t HDMI_GC_CONT;
|
||||
uint32_t HDMI_GC_SEND;
|
||||
uint32_t HDMI_NULL_SEND;
|
||||
uint32_t HDMI_DATA_SCRAMBLE_EN;
|
||||
uint32_t HDMI_AUDIO_INFO_SEND;
|
||||
uint32_t AFMT_AUDIO_INFO_UPDATE;
|
||||
uint32_t HDMI_AUDIO_INFO_LINE;
|
||||
uint32_t HDMI_GC_AVMUTE;
|
||||
uint32_t DP_MSE_RATE_X;
|
||||
uint32_t DP_MSE_RATE_Y;
|
||||
uint32_t DP_MSE_RATE_UPDATE_PENDING;
|
||||
uint32_t DP_SEC_GSP0_ENABLE;
|
||||
uint32_t DP_SEC_STREAM_ENABLE;
|
||||
uint32_t DP_SEC_GSP1_ENABLE;
|
||||
uint32_t DP_SEC_GSP2_ENABLE;
|
||||
uint32_t DP_SEC_GSP3_ENABLE;
|
||||
uint32_t DP_SEC_GSP4_ENABLE;
|
||||
uint32_t DP_SEC_GSP5_ENABLE;
|
||||
uint32_t DP_SEC_GSP6_ENABLE;
|
||||
uint32_t DP_SEC_GSP7_ENABLE;
|
||||
uint32_t DP_SEC_MPG_ENABLE;
|
||||
uint32_t DP_VID_STREAM_DIS_DEFER;
|
||||
uint32_t DP_VID_STREAM_ENABLE;
|
||||
uint32_t DP_VID_STREAM_STATUS;
|
||||
uint32_t DP_STEER_FIFO_RESET;
|
||||
uint32_t DP_VID_M_N_GEN_EN;
|
||||
uint32_t DP_VID_N;
|
||||
uint32_t DP_VID_M;
|
||||
uint32_t DIG_START;
|
||||
uint32_t AFMT_AUDIO_SRC_SELECT;
|
||||
uint32_t AFMT_AUDIO_CHANNEL_ENABLE;
|
||||
uint32_t HDMI_AUDIO_PACKETS_PER_LINE;
|
||||
uint32_t HDMI_AUDIO_DELAY_EN;
|
||||
uint32_t AFMT_60958_CS_UPDATE;
|
||||
uint32_t AFMT_AUDIO_LAYOUT_OVRD;
|
||||
uint32_t AFMT_60958_OSF_OVRD;
|
||||
uint32_t HDMI_ACR_AUTO_SEND;
|
||||
uint32_t HDMI_ACR_SOURCE;
|
||||
uint32_t HDMI_ACR_AUDIO_PRIORITY;
|
||||
uint32_t HDMI_ACR_CTS_32;
|
||||
uint32_t HDMI_ACR_N_32;
|
||||
uint32_t HDMI_ACR_CTS_44;
|
||||
uint32_t HDMI_ACR_N_44;
|
||||
uint32_t HDMI_ACR_CTS_48;
|
||||
uint32_t HDMI_ACR_N_48;
|
||||
uint32_t AFMT_60958_CS_CHANNEL_NUMBER_L;
|
||||
uint32_t AFMT_60958_CS_CLOCK_ACCURACY;
|
||||
uint32_t AFMT_60958_CS_CHANNEL_NUMBER_R;
|
||||
uint32_t AFMT_60958_CS_CHANNEL_NUMBER_2;
|
||||
uint32_t AFMT_60958_CS_CHANNEL_NUMBER_3;
|
||||
uint32_t AFMT_60958_CS_CHANNEL_NUMBER_4;
|
||||
uint32_t AFMT_60958_CS_CHANNEL_NUMBER_5;
|
||||
uint32_t AFMT_60958_CS_CHANNEL_NUMBER_6;
|
||||
uint32_t AFMT_60958_CS_CHANNEL_NUMBER_7;
|
||||
uint32_t DP_SEC_AUD_N;
|
||||
uint32_t DP_SEC_TIMESTAMP_MODE;
|
||||
uint32_t DP_SEC_ASP_ENABLE;
|
||||
uint32_t DP_SEC_ATP_ENABLE;
|
||||
uint32_t DP_SEC_AIP_ENABLE;
|
||||
uint32_t DP_SEC_ACM_ENABLE;
|
||||
uint32_t AFMT_AUDIO_SAMPLE_SEND;
|
||||
uint32_t AFMT_AUDIO_CLOCK_EN;
|
||||
uint32_t TMDS_PIXEL_ENCODING;
|
||||
uint32_t DIG_STEREOSYNC_SELECT;
|
||||
uint32_t DIG_STEREOSYNC_GATE_EN;
|
||||
uint32_t TMDS_COLOR_FORMAT;
|
||||
uint32_t DP_DB_DISABLE;
|
||||
uint32_t DP_MSA_MISC0;
|
||||
uint32_t DP_MSA_HTOTAL;
|
||||
uint32_t DP_MSA_VTOTAL;
|
||||
uint32_t DP_MSA_HSTART;
|
||||
uint32_t DP_MSA_VSTART;
|
||||
uint32_t DP_MSA_HSYNCWIDTH;
|
||||
uint32_t DP_MSA_HSYNCPOLARITY;
|
||||
uint32_t DP_MSA_VSYNCWIDTH;
|
||||
uint32_t DP_MSA_VSYNCPOLARITY;
|
||||
uint32_t DP_MSA_HWIDTH;
|
||||
uint32_t DP_MSA_VHEIGHT;
|
||||
uint32_t HDMI_DB_DISABLE;
|
||||
uint32_t DP_VID_N_MUL;
|
||||
uint32_t DP_VID_M_DOUBLE_VALUE_EN;
|
||||
};
|
||||
|
||||
struct dcn10_stream_enc_registers {
|
||||
uint32_t AFMT_CNTL;
|
||||
uint32_t AFMT_AVI_INFO0;
|
||||
uint32_t AFMT_AVI_INFO1;
|
||||
uint32_t AFMT_AVI_INFO2;
|
||||
uint32_t AFMT_AVI_INFO3;
|
||||
uint32_t AFMT_GENERIC_0;
|
||||
uint32_t AFMT_GENERIC_1;
|
||||
uint32_t AFMT_GENERIC_2;
|
||||
uint32_t AFMT_GENERIC_3;
|
||||
uint32_t AFMT_GENERIC_4;
|
||||
uint32_t AFMT_GENERIC_5;
|
||||
uint32_t AFMT_GENERIC_6;
|
||||
uint32_t AFMT_GENERIC_7;
|
||||
uint32_t AFMT_GENERIC_HDR;
|
||||
uint32_t AFMT_INFOFRAME_CONTROL0;
|
||||
uint32_t AFMT_VBI_PACKET_CONTROL;
|
||||
uint32_t AFMT_VBI_PACKET_CONTROL1;
|
||||
uint32_t AFMT_AUDIO_PACKET_CONTROL;
|
||||
uint32_t AFMT_AUDIO_PACKET_CONTROL2;
|
||||
uint32_t AFMT_AUDIO_SRC_CONTROL;
|
||||
uint32_t AFMT_60958_0;
|
||||
uint32_t AFMT_60958_1;
|
||||
uint32_t AFMT_60958_2;
|
||||
uint32_t DIG_FE_CNTL;
|
||||
uint32_t DP_MSE_RATE_CNTL;
|
||||
uint32_t DP_MSE_RATE_UPDATE;
|
||||
uint32_t DP_PIXEL_FORMAT;
|
||||
uint32_t DP_SEC_CNTL;
|
||||
uint32_t DP_STEER_FIFO;
|
||||
uint32_t DP_VID_M;
|
||||
uint32_t DP_VID_N;
|
||||
uint32_t DP_VID_STREAM_CNTL;
|
||||
uint32_t DP_VID_TIMING;
|
||||
uint32_t DP_SEC_AUD_N;
|
||||
uint32_t DP_SEC_TIMESTAMP;
|
||||
uint32_t HDMI_CONTROL;
|
||||
uint32_t HDMI_GC;
|
||||
uint32_t HDMI_GENERIC_PACKET_CONTROL0;
|
||||
uint32_t HDMI_GENERIC_PACKET_CONTROL1;
|
||||
uint32_t HDMI_GENERIC_PACKET_CONTROL2;
|
||||
uint32_t HDMI_GENERIC_PACKET_CONTROL3;
|
||||
uint32_t HDMI_GENERIC_PACKET_CONTROL4;
|
||||
uint32_t HDMI_GENERIC_PACKET_CONTROL5;
|
||||
uint32_t HDMI_INFOFRAME_CONTROL0;
|
||||
uint32_t HDMI_INFOFRAME_CONTROL1;
|
||||
uint32_t HDMI_VBI_PACKET_CONTROL;
|
||||
uint32_t HDMI_AUDIO_PACKET_CONTROL;
|
||||
uint32_t HDMI_ACR_PACKET_CONTROL;
|
||||
uint32_t HDMI_ACR_32_0;
|
||||
uint32_t HDMI_ACR_32_1;
|
||||
uint32_t HDMI_ACR_44_0;
|
||||
uint32_t HDMI_ACR_44_1;
|
||||
uint32_t HDMI_ACR_48_0;
|
||||
uint32_t HDMI_ACR_48_1;
|
||||
uint32_t TMDS_CNTL;
|
||||
uint32_t DP_DB_CNTL;
|
||||
uint32_t DP_MSA_MISC;
|
||||
uint32_t DP_MSA_COLORIMETRY;
|
||||
uint32_t DP_MSA_TIMING_PARAM1;
|
||||
uint32_t DP_MSA_TIMING_PARAM2;
|
||||
uint32_t DP_MSA_TIMING_PARAM3;
|
||||
uint32_t DP_MSA_TIMING_PARAM4;
|
||||
uint32_t HDMI_DB_CONTROL;
|
||||
};
|
||||
|
||||
struct dcn10_stream_encoder {
|
||||
struct stream_encoder base;
|
||||
const struct dcn10_stream_enc_registers *regs;
|
||||
const struct dcn10_stream_encoder_shift *se_shift;
|
||||
const struct dcn10_stream_encoder_mask *se_mask;
|
||||
};
|
||||
|
||||
void dcn10_stream_encoder_construct(
|
||||
struct dcn10_stream_encoder *enc1,
|
||||
struct dc_context *ctx,
|
||||
struct dc_bios *bp,
|
||||
enum engine_id eng_id,
|
||||
const struct dcn10_stream_enc_registers *regs,
|
||||
const struct dcn10_stream_encoder_shift *se_shift,
|
||||
const struct dcn10_stream_encoder_mask *se_mask);
|
||||
|
||||
#endif /* __DC_STREAM_ENCODER_DCN10_H__ */
|
||||
Loading…
Reference in New Issue
Block a user