DaVinci: DM365: Adding entries for DM365 IRQ's

This patch adds definitions for some DM365 IRQs that are used by
the codecs. Codecs will also use the IRQs.
Entries are being added to enable/disable IRQ's.
There is no use as such for these entires in the kernel itself.
Instead these will be used by the "linuxutils" package of the DVSDK.

For further information on IRQ muxing refer to
http://focus.ti.com/lit/ug/sprufg5a/sprufg5a.pdf

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Sneha Narnakaje <nsnehaprabha@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
This commit is contained in:
Sandeep Paulraj 2009-08-18 11:08:27 -04:00 committed by Kevin Hilman
parent 1aebb50e06
commit 0c30e0d31b
3 changed files with 19 additions and 0 deletions

View File

@ -595,6 +595,14 @@ INT_CFG(DM365, INT_EMAC_RXTHRESH, 14, 1, 1, false)
INT_CFG(DM365, INT_EMAC_RXPULSE, 15, 1, 1, false)
INT_CFG(DM365, INT_EMAC_TXPULSE, 16, 1, 1, false)
INT_CFG(DM365, INT_EMAC_MISCPULSE, 17, 1, 1, false)
INT_CFG(DM365, INT_IMX0_ENABLE, 0, 1, 0, false)
INT_CFG(DM365, INT_IMX0_DISABLE, 0, 1, 1, false)
INT_CFG(DM365, INT_HDVICP_ENABLE, 0, 1, 1, false)
INT_CFG(DM365, INT_HDVICP_DISABLE, 0, 1, 0, false)
INT_CFG(DM365, INT_IMX1_ENABLE, 24, 1, 1, false)
INT_CFG(DM365, INT_IMX1_DISABLE, 24, 1, 0, false)
INT_CFG(DM365, INT_NSF_ENABLE, 25, 1, 1, false)
INT_CFG(DM365, INT_NSF_DISABLE, 25, 1, 0, false)
#endif
};

View File

@ -205,6 +205,9 @@
/* DaVinci DM365-specific Interrupts */
#define IRQ_DM365_INSFINT 7
#define IRQ_DM365_IMXINT1 8
#define IRQ_DM365_IMXINT0 10
#define IRQ_DM365_KLD_ARMINT 10
#define IRQ_DM365_IMCOPINT 11
#define IRQ_DM365_RTOINT 13
#define IRQ_DM365_TINT5 14

View File

@ -301,6 +301,14 @@ enum davinci_dm365_index {
DM365_INT_EMAC_RXPULSE,
DM365_INT_EMAC_TXPULSE,
DM365_INT_EMAC_MISCPULSE,
DM365_INT_IMX0_ENABLE,
DM365_INT_IMX0_DISABLE,
DM365_INT_HDVICP_ENABLE,
DM365_INT_HDVICP_DISABLE,
DM365_INT_IMX1_ENABLE,
DM365_INT_IMX1_DISABLE,
DM365_INT_NSF_ENABLE,
DM365_INT_NSF_DISABLE,
/* EDMA event muxing */
DM365_EVT2_ASP_TX,