forked from Minki/linux
net: w5100: support W5200
This adds support for W5200 chip. W5100 and W5200 have similar memory map although some of their offsets are different. The register access sequences between them are different but w5100 driver has abstraction layer for difference bus interface modes so it is easy to add W5200 support to w5100 and w5100-spi drivers. Signed-off-by: Akinobu Mita <akinobu.mita@gmail.com> Cc: Mike Sinkovsky <msink@permonline.ru> Cc: David S. Miller <davem@davemloft.net> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Akinobu Mita
David S. Miller
parent
630cf09751
commit
0c165ff2d8
@ -70,7 +70,7 @@ config WIZNET_BUS_ANY
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endchoice
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config WIZNET_W5100_SPI
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tristate "WIZnet W5100 Ethernet support for SPI mode"
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tristate "WIZnet W5100/W5200 Ethernet support for SPI mode"
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depends on WIZNET_BUS_ANY
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depends on SPI
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---help---
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@ -1,9 +1,13 @@
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/*
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* Ethernet driver for the WIZnet W5100 chip.
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* Ethernet driver for the WIZnet W5100/W5200 chip.
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*
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* Copyright (C) 2016 Akinobu Mita <akinobu.mita@gmail.com>
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*
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* Licensed under the GPL-2 or later.
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*
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* Datasheet:
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* http://www.wiznet.co.kr/wp-content/uploads/wiznethome/Chip/W5100/Document/W5100_Datasheet_v1.2.6.pdf
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* http://wiznethome.cafe24.com/wp-content/uploads/wiznethome/Chip/W5200/Documents/W5200_DS_V140E.pdf
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*/
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#include <linux/kernel.h>
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@ -95,6 +99,7 @@ static int w5100_spi_writebulk(struct net_device *ndev, u16 addr, const u8 *buf,
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static const struct w5100_ops w5100_spi_ops = {
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.may_sleep = true,
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.chip_id = W5100,
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.read = w5100_spi_read,
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.write = w5100_spi_write,
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.read16 = w5100_spi_read16,
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@ -103,10 +108,168 @@ static const struct w5100_ops w5100_spi_ops = {
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.writebulk = w5100_spi_writebulk,
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};
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#define W5200_SPI_WRITE_OPCODE 0x80
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struct w5200_spi_priv {
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/* Serialize access to cmd_buf */
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struct mutex cmd_lock;
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/* DMA (thus cache coherency maintenance) requires the
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* transfer buffers to live in their own cache lines.
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*/
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u8 cmd_buf[4] ____cacheline_aligned;
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};
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static struct w5200_spi_priv *w5200_spi_priv(struct net_device *ndev)
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{
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return w5100_ops_priv(ndev);
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}
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static int w5200_spi_init(struct net_device *ndev)
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{
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struct w5200_spi_priv *spi_priv = w5200_spi_priv(ndev);
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mutex_init(&spi_priv->cmd_lock);
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return 0;
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}
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static int w5200_spi_read(struct net_device *ndev, u16 addr)
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{
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struct spi_device *spi = to_spi_device(ndev->dev.parent);
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u8 cmd[4] = { addr >> 8, addr & 0xff, 0, 1 };
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u8 data;
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int ret;
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ret = spi_write_then_read(spi, cmd, sizeof(cmd), &data, 1);
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return ret ? ret : data;
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}
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static int w5200_spi_write(struct net_device *ndev, u16 addr, u8 data)
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{
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struct spi_device *spi = to_spi_device(ndev->dev.parent);
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u8 cmd[5] = { addr >> 8, addr & 0xff, W5200_SPI_WRITE_OPCODE, 1, data };
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return spi_write_then_read(spi, cmd, sizeof(cmd), NULL, 0);
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}
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static int w5200_spi_read16(struct net_device *ndev, u16 addr)
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{
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struct spi_device *spi = to_spi_device(ndev->dev.parent);
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u8 cmd[4] = { addr >> 8, addr & 0xff, 0, 2 };
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__be16 data;
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int ret;
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ret = spi_write_then_read(spi, cmd, sizeof(cmd), &data, sizeof(data));
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return ret ? ret : be16_to_cpu(data);
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}
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static int w5200_spi_write16(struct net_device *ndev, u16 addr, u16 data)
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{
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struct spi_device *spi = to_spi_device(ndev->dev.parent);
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u8 cmd[6] = {
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addr >> 8, addr & 0xff,
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W5200_SPI_WRITE_OPCODE, 2,
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data >> 8, data & 0xff
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};
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return spi_write_then_read(spi, cmd, sizeof(cmd), NULL, 0);
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}
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static int w5200_spi_readbulk(struct net_device *ndev, u16 addr, u8 *buf,
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int len)
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{
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struct spi_device *spi = to_spi_device(ndev->dev.parent);
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struct w5200_spi_priv *spi_priv = w5200_spi_priv(ndev);
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struct spi_transfer xfer[] = {
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{
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.tx_buf = spi_priv->cmd_buf,
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.len = sizeof(spi_priv->cmd_buf),
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},
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{
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.rx_buf = buf,
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.len = len,
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},
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};
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int ret;
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mutex_lock(&spi_priv->cmd_lock);
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spi_priv->cmd_buf[0] = addr >> 8;
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spi_priv->cmd_buf[1] = addr;
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spi_priv->cmd_buf[2] = len >> 8;
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spi_priv->cmd_buf[3] = len;
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ret = spi_sync_transfer(spi, xfer, ARRAY_SIZE(xfer));
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mutex_unlock(&spi_priv->cmd_lock);
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return ret;
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}
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static int w5200_spi_writebulk(struct net_device *ndev, u16 addr, const u8 *buf,
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int len)
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{
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struct spi_device *spi = to_spi_device(ndev->dev.parent);
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struct w5200_spi_priv *spi_priv = w5200_spi_priv(ndev);
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struct spi_transfer xfer[] = {
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{
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.tx_buf = spi_priv->cmd_buf,
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.len = sizeof(spi_priv->cmd_buf),
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},
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{
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.tx_buf = buf,
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.len = len,
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},
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};
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int ret;
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mutex_lock(&spi_priv->cmd_lock);
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spi_priv->cmd_buf[0] = addr >> 8;
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spi_priv->cmd_buf[1] = addr;
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spi_priv->cmd_buf[2] = W5200_SPI_WRITE_OPCODE | (len >> 8);
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spi_priv->cmd_buf[3] = len;
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ret = spi_sync_transfer(spi, xfer, ARRAY_SIZE(xfer));
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mutex_unlock(&spi_priv->cmd_lock);
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return ret;
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}
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static const struct w5100_ops w5200_ops = {
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.may_sleep = true,
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.chip_id = W5200,
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.read = w5200_spi_read,
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.write = w5200_spi_write,
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.read16 = w5200_spi_read16,
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.write16 = w5200_spi_write16,
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.readbulk = w5200_spi_readbulk,
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.writebulk = w5200_spi_writebulk,
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.init = w5200_spi_init,
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};
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static int w5100_spi_probe(struct spi_device *spi)
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{
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return w5100_probe(&spi->dev, &w5100_spi_ops, 0, NULL, spi->irq,
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-EINVAL);
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const struct spi_device_id *id = spi_get_device_id(spi);
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const struct w5100_ops *ops;
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int priv_size;
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switch (id->driver_data) {
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case W5100:
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ops = &w5100_spi_ops;
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priv_size = 0;
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break;
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case W5200:
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ops = &w5200_ops;
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priv_size = sizeof(struct w5200_spi_priv);
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break;
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default:
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return -EINVAL;
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}
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return w5100_probe(&spi->dev, ops, priv_size, NULL, spi->irq, -EINVAL);
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}
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static int w5100_spi_remove(struct spi_device *spi)
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@ -115,7 +278,8 @@ static int w5100_spi_remove(struct spi_device *spi)
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}
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static const struct spi_device_id w5100_spi_ids[] = {
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{ "w5100", 0 },
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{ "w5100", W5100 },
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{ "w5200", W5200 },
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{}
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};
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MODULE_DEVICE_TABLE(spi, w5100_spi_ids);
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@ -131,6 +295,6 @@ static struct spi_driver w5100_spi_driver = {
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};
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module_spi_driver(w5100_spi_driver);
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MODULE_DESCRIPTION("WIZnet W5100 Ethernet driver for SPI mode");
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MODULE_DESCRIPTION("WIZnet W5100/W5200 Ethernet driver for SPI mode");
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MODULE_AUTHOR("Akinobu Mita <akinobu.mita@gmail.com>");
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MODULE_LICENSE("GPL");
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@ -38,7 +38,7 @@ MODULE_ALIAS("platform:"DRV_NAME);
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MODULE_LICENSE("GPL");
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/*
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* Registers
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* W5100 and W5100 common registers
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*/
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#define W5100_COMMON_REGS 0x0000
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#define W5100_MR 0x0000 /* Mode Register */
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@ -52,36 +52,68 @@ MODULE_LICENSE("GPL");
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#define IR_S0 0x01 /* S0 interrupt */
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#define W5100_RTR 0x0017 /* Retry Time-value Register */
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#define RTR_DEFAULT 2000 /* =0x07d0 (2000) */
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#define W5100_RMSR 0x001a /* Receive Memory Size */
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#define W5100_TMSR 0x001b /* Transmit Memory Size */
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#define W5100_COMMON_REGS_LEN 0x0040
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#define W5100_S0_REGS 0x0400
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#define W5100_S0_MR 0x0400 /* S0 Mode Register */
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#define W5100_Sn_MR 0x0000 /* Sn Mode Register */
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#define W5100_Sn_CR 0x0001 /* Sn Command Register */
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#define W5100_Sn_IR 0x0002 /* Sn Interrupt Register */
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#define W5100_Sn_SR 0x0003 /* Sn Status Register */
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#define W5100_Sn_TX_FSR 0x0020 /* Sn Transmit free memory size */
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#define W5100_Sn_TX_RD 0x0022 /* Sn Transmit memory read pointer */
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#define W5100_Sn_TX_WR 0x0024 /* Sn Transmit memory write pointer */
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#define W5100_Sn_RX_RSR 0x0026 /* Sn Receive free memory size */
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#define W5100_Sn_RX_RD 0x0028 /* Sn Receive memory read pointer */
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#define S0_REGS(priv) (is_w5200(priv) ? W5200_S0_REGS : W5100_S0_REGS)
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#define W5100_S0_MR(priv) (S0_REGS(priv) + W5100_Sn_MR)
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#define S0_MR_MACRAW 0x04 /* MAC RAW mode (promiscuous) */
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#define S0_MR_MACRAW_MF 0x44 /* MAC RAW mode (filtered) */
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#define W5100_S0_CR 0x0401 /* S0 Command Register */
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#define W5100_S0_CR(priv) (S0_REGS(priv) + W5100_Sn_CR)
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#define S0_CR_OPEN 0x01 /* OPEN command */
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#define S0_CR_CLOSE 0x10 /* CLOSE command */
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#define S0_CR_SEND 0x20 /* SEND command */
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#define S0_CR_RECV 0x40 /* RECV command */
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#define W5100_S0_IR 0x0402 /* S0 Interrupt Register */
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#define W5100_S0_IR(priv) (S0_REGS(priv) + W5100_Sn_IR)
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#define S0_IR_SENDOK 0x10 /* complete sending */
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#define S0_IR_RECV 0x04 /* receiving data */
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#define W5100_S0_SR 0x0403 /* S0 Status Register */
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#define W5100_S0_SR(priv) (S0_REGS(priv) + W5100_Sn_SR)
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#define S0_SR_MACRAW 0x42 /* mac raw mode */
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#define W5100_S0_TX_FSR 0x0420 /* S0 Transmit free memory size */
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#define W5100_S0_TX_RD 0x0422 /* S0 Transmit memory read pointer */
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#define W5100_S0_TX_WR 0x0424 /* S0 Transmit memory write pointer */
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#define W5100_S0_RX_RSR 0x0426 /* S0 Receive free memory size */
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#define W5100_S0_RX_RD 0x0428 /* S0 Receive memory read pointer */
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#define W5100_S0_TX_FSR(priv) (S0_REGS(priv) + W5100_Sn_TX_FSR)
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#define W5100_S0_TX_RD(priv) (S0_REGS(priv) + W5100_Sn_TX_RD)
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#define W5100_S0_TX_WR(priv) (S0_REGS(priv) + W5100_Sn_TX_WR)
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#define W5100_S0_RX_RSR(priv) (S0_REGS(priv) + W5100_Sn_RX_RSR)
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#define W5100_S0_RX_RD(priv) (S0_REGS(priv) + W5100_Sn_RX_RD)
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#define W5100_S0_REGS_LEN 0x0040
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/*
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* W5100 specific registers
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*/
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#define W5100_RMSR 0x001a /* Receive Memory Size */
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#define W5100_TMSR 0x001b /* Transmit Memory Size */
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#define W5100_S0_REGS 0x0400
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#define W5100_TX_MEM_START 0x4000
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#define W5100_TX_MEM_SIZE 0x2000
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#define W5100_RX_MEM_START 0x6000
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#define W5100_RX_MEM_SIZE 0x2000
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/*
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* W5200 specific registers
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*/
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#define W5200_S0_REGS 0x4000
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#define W5200_Sn_RXMEM_SIZE(n) (0x401e + (n) * 0x0100) /* Sn RX Memory Size */
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#define W5200_Sn_TXMEM_SIZE(n) (0x401f + (n) * 0x0100) /* Sn TX Memory Size */
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#define W5200_S0_IMR 0x402c /* S0 Interrupt Mask Register */
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#define W5200_TX_MEM_START 0x8000
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#define W5200_TX_MEM_SIZE 0x4000
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#define W5200_RX_MEM_START 0xc000
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#define W5200_RX_MEM_SIZE 0x4000
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/*
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* Device driver private data structure
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*/
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@ -105,6 +137,11 @@ struct w5100_priv {
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struct work_struct restart_work;
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};
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static inline bool is_w5200(struct w5100_priv *priv)
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{
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return priv->ops->chip_id == W5200;
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}
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/************************************************************************
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*
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* Lowlevel I/O functions
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@ -217,6 +254,7 @@ static int w5100_mmio_init(struct net_device *ndev)
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}
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static const struct w5100_ops w5100_mmio_direct_ops = {
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.chip_id = W5100,
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.read = w5100_read_direct,
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.write = w5100_write_direct,
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.read16 = w5100_read16_direct,
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@ -341,6 +379,7 @@ static int w5100_reset_indirect(struct net_device *ndev)
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}
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static const struct w5100_ops w5100_mmio_indirect_ops = {
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.chip_id = W5100,
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.read = w5100_read_indirect,
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.write = w5100_write_indirect,
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.read16 = w5100_read16_indirect,
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@ -457,20 +496,24 @@ static int w5100_readbuf(struct w5100_priv *priv, u16 offset, u8 *buf, int len)
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u16 addr;
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int remain = 0;
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int ret;
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const u16 mem_start =
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is_w5200(priv) ? W5200_RX_MEM_START : W5100_RX_MEM_START;
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const u16 mem_size =
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is_w5200(priv) ? W5200_RX_MEM_SIZE : W5100_RX_MEM_SIZE;
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offset %= W5100_RX_MEM_SIZE;
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addr = W5100_RX_MEM_START + offset;
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offset %= mem_size;
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addr = mem_start + offset;
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if (offset + len > W5100_RX_MEM_SIZE) {
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remain = (offset + len) % W5100_RX_MEM_SIZE;
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len = W5100_RX_MEM_SIZE - offset;
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if (offset + len > mem_size) {
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remain = (offset + len) % mem_size;
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len = mem_size - offset;
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}
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ret = w5100_readbulk(priv, addr, buf, len);
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if (ret || !remain)
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return ret;
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return w5100_readbulk(priv, W5100_RX_MEM_START, buf + len, remain);
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return w5100_readbulk(priv, mem_start, buf + len, remain);
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}
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static int w5100_writebuf(struct w5100_priv *priv, u16 offset, const u8 *buf,
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@ -479,20 +522,24 @@ static int w5100_writebuf(struct w5100_priv *priv, u16 offset, const u8 *buf,
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u16 addr;
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int ret;
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int remain = 0;
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const u16 mem_start =
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is_w5200(priv) ? W5200_TX_MEM_START : W5100_TX_MEM_START;
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const u16 mem_size =
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is_w5200(priv) ? W5200_TX_MEM_SIZE : W5100_TX_MEM_SIZE;
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offset %= W5100_TX_MEM_SIZE;
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addr = W5100_TX_MEM_START + offset;
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offset %= mem_size;
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addr = mem_start + offset;
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if (offset + len > W5100_TX_MEM_SIZE) {
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remain = (offset + len) % W5100_TX_MEM_SIZE;
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len = W5100_TX_MEM_SIZE - offset;
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if (offset + len > mem_size) {
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remain = (offset + len) % mem_size;
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len = mem_size - offset;
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}
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ret = w5100_writebulk(priv, addr, buf, len);
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if (ret || !remain)
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return ret;
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return w5100_writebulk(priv, W5100_TX_MEM_START, buf + len, remain);
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return w5100_writebulk(priv, mem_start, buf + len, remain);
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}
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static int w5100_reset(struct w5100_priv *priv)
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@ -511,11 +558,11 @@ static int w5100_command(struct w5100_priv *priv, u16 cmd)
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{
|
||||
unsigned long timeout;
|
||||
|
||||
w5100_write(priv, W5100_S0_CR, cmd);
|
||||
w5100_write(priv, W5100_S0_CR(priv), cmd);
|
||||
|
||||
timeout = jiffies + msecs_to_jiffies(100);
|
||||
|
||||
while (w5100_read(priv, W5100_S0_CR) != 0) {
|
||||
while (w5100_read(priv, W5100_S0_CR(priv)) != 0) {
|
||||
if (time_after(jiffies, timeout))
|
||||
return -EIO;
|
||||
cpu_relax();
|
||||
@ -531,13 +578,8 @@ static void w5100_write_macaddr(struct w5100_priv *priv)
|
||||
w5100_writebulk(priv, W5100_SHAR, ndev->dev_addr, ETH_ALEN);
|
||||
}
|
||||
|
||||
static void w5100_hw_reset(struct w5100_priv *priv)
|
||||
static void w5100_memory_configure(struct w5100_priv *priv)
|
||||
{
|
||||
w5100_reset(priv);
|
||||
|
||||
w5100_write(priv, W5100_IMR, 0);
|
||||
w5100_write_macaddr(priv);
|
||||
|
||||
/* Configure 16K of internal memory
|
||||
* as 8K RX buffer and 8K TX buffer
|
||||
*/
|
||||
@ -545,9 +587,38 @@ static void w5100_hw_reset(struct w5100_priv *priv)
|
||||
w5100_write(priv, W5100_TMSR, 0x03);
|
||||
}
|
||||
|
||||
static void w5200_memory_configure(struct w5100_priv *priv)
|
||||
{
|
||||
int i;
|
||||
|
||||
/* Configure internal RX memory as 16K RX buffer and
|
||||
* internal TX memory as 16K TX buffer
|
||||
*/
|
||||
w5100_write(priv, W5200_Sn_RXMEM_SIZE(0), 0x10);
|
||||
w5100_write(priv, W5200_Sn_TXMEM_SIZE(0), 0x10);
|
||||
|
||||
for (i = 1; i < 8; i++) {
|
||||
w5100_write(priv, W5200_Sn_RXMEM_SIZE(i), 0);
|
||||
w5100_write(priv, W5200_Sn_TXMEM_SIZE(i), 0);
|
||||
}
|
||||
}
|
||||
|
||||
static void w5100_hw_reset(struct w5100_priv *priv)
|
||||
{
|
||||
w5100_reset(priv);
|
||||
|
||||
w5100_write(priv, W5100_IMR, 0);
|
||||
w5100_write_macaddr(priv);
|
||||
|
||||
if (is_w5200(priv))
|
||||
w5200_memory_configure(priv);
|
||||
else
|
||||
w5100_memory_configure(priv);
|
||||
}
|
||||
|
||||
static void w5100_hw_start(struct w5100_priv *priv)
|
||||
{
|
||||
w5100_write(priv, W5100_S0_MR, priv->promisc ?
|
||||
w5100_write(priv, W5100_S0_MR(priv), priv->promisc ?
|
||||
S0_MR_MACRAW : S0_MR_MACRAW_MF);
|
||||
w5100_command(priv, S0_CR_OPEN);
|
||||
w5100_write(priv, W5100_IMR, IR_S0);
|
||||
@ -611,7 +682,7 @@ static void w5100_get_regs(struct net_device *ndev,
|
||||
regs->version = 1;
|
||||
w5100_readbulk(priv, W5100_COMMON_REGS, buf, W5100_COMMON_REGS_LEN);
|
||||
buf += W5100_COMMON_REGS_LEN;
|
||||
w5100_readbulk(priv, W5100_S0_REGS, buf, W5100_S0_REGS_LEN);
|
||||
w5100_readbulk(priv, S0_REGS(priv), buf, W5100_S0_REGS_LEN);
|
||||
}
|
||||
|
||||
static void w5100_restart(struct net_device *ndev)
|
||||
@ -649,9 +720,9 @@ static void w5100_tx_skb(struct net_device *ndev, struct sk_buff *skb)
|
||||
struct w5100_priv *priv = netdev_priv(ndev);
|
||||
u16 offset;
|
||||
|
||||
offset = w5100_read16(priv, W5100_S0_TX_WR);
|
||||
offset = w5100_read16(priv, W5100_S0_TX_WR(priv));
|
||||
w5100_writebuf(priv, offset, skb->data, skb->len);
|
||||
w5100_write16(priv, W5100_S0_TX_WR, offset + skb->len);
|
||||
w5100_write16(priv, W5100_S0_TX_WR(priv), offset + skb->len);
|
||||
ndev->stats.tx_bytes += skb->len;
|
||||
ndev->stats.tx_packets++;
|
||||
dev_kfree_skb(skb);
|
||||
@ -696,18 +767,18 @@ static struct sk_buff *w5100_rx_skb(struct net_device *ndev)
|
||||
u16 rx_len;
|
||||
u16 offset;
|
||||
u8 header[2];
|
||||
u16 rx_buf_len = w5100_read16(priv, W5100_S0_RX_RSR);
|
||||
u16 rx_buf_len = w5100_read16(priv, W5100_S0_RX_RSR(priv));
|
||||
|
||||
if (rx_buf_len == 0)
|
||||
return NULL;
|
||||
|
||||
offset = w5100_read16(priv, W5100_S0_RX_RD);
|
||||
offset = w5100_read16(priv, W5100_S0_RX_RD(priv));
|
||||
w5100_readbuf(priv, offset, header, 2);
|
||||
rx_len = get_unaligned_be16(header) - 2;
|
||||
|
||||
skb = netdev_alloc_skb_ip_align(ndev, rx_len);
|
||||
if (unlikely(!skb)) {
|
||||
w5100_write16(priv, W5100_S0_RX_RD, offset + rx_buf_len);
|
||||
w5100_write16(priv, W5100_S0_RX_RD(priv), offset + rx_buf_len);
|
||||
w5100_command(priv, S0_CR_RECV);
|
||||
ndev->stats.rx_dropped++;
|
||||
return NULL;
|
||||
@ -715,7 +786,7 @@ static struct sk_buff *w5100_rx_skb(struct net_device *ndev)
|
||||
|
||||
skb_put(skb, rx_len);
|
||||
w5100_readbuf(priv, offset + 2, skb->data, rx_len);
|
||||
w5100_write16(priv, W5100_S0_RX_RD, offset + 2 + rx_len);
|
||||
w5100_write16(priv, W5100_S0_RX_RD(priv), offset + 2 + rx_len);
|
||||
w5100_command(priv, S0_CR_RECV);
|
||||
skb->protocol = eth_type_trans(skb, ndev);
|
||||
|
||||
@ -764,10 +835,10 @@ static irqreturn_t w5100_interrupt(int irq, void *ndev_instance)
|
||||
struct net_device *ndev = ndev_instance;
|
||||
struct w5100_priv *priv = netdev_priv(ndev);
|
||||
|
||||
int ir = w5100_read(priv, W5100_S0_IR);
|
||||
int ir = w5100_read(priv, W5100_S0_IR(priv));
|
||||
if (!ir)
|
||||
return IRQ_NONE;
|
||||
w5100_write(priv, W5100_S0_IR, ir);
|
||||
w5100_write(priv, W5100_S0_IR(priv), ir);
|
||||
|
||||
if (ir & S0_IR_SENDOK) {
|
||||
netif_dbg(priv, tx_done, ndev, "tx done\n");
|
||||
|
||||
@ -7,8 +7,14 @@
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
||||
enum {
|
||||
W5100,
|
||||
W5200,
|
||||
};
|
||||
|
||||
struct w5100_ops {
|
||||
bool may_sleep;
|
||||
int chip_id;
|
||||
int (*read)(struct net_device *ndev, u16 addr);
|
||||
int (*write)(struct net_device *ndev, u16 addr, u8 data);
|
||||
int (*read16)(struct net_device *ndev, u16 addr);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user