dt-bindings: power: Convert imx gpc to json-schema
Convert the i.MX GPC binding to DT schema format using json-schema >From latest reference manual, there is actually ONLY 1 interrupt for GPC, so the additional GPC interrupt is removed. Consumer's example is also removed since it is NOT that useful. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Rob Herring <robh@kernel.org>
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Anson Huang
Rob Herring
parent
8f8986e932
commit
0c03fa00fd
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Freescale i.MX General Power Controller
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=======================================
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The i.MX6 General Power Control (GPC) block contains DVFS load tracking
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counters and Power Gating Control (PGC).
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Required properties:
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- compatible: Should be one of the following:
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- fsl,imx6q-gpc
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- fsl,imx6qp-gpc
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- fsl,imx6sl-gpc
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- fsl,imx6sx-gpc
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- reg: should be register base and length as documented in the
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datasheet
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- interrupts: Should contain one interrupt specifier for the GPC interrupt
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- clocks: Must contain an entry for each entry in clock-names.
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See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
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- clock-names: Must include the following entries:
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- ipg
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The power domains are generic power domain providers as documented in
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Documentation/devicetree/bindings/power/power-domain.yaml. They are described as
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subnodes of the power gating controller 'pgc' node of the GPC and should
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contain the following:
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Required properties:
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- reg: Must contain the DOMAIN_INDEX of this power domain
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The following DOMAIN_INDEX values are valid for i.MX6Q:
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ARM_DOMAIN 0
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PU_DOMAIN 1
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The following additional DOMAIN_INDEX value is valid for i.MX6SL:
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DISPLAY_DOMAIN 2
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The following additional DOMAIN_INDEX value is valid for i.MX6SX:
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PCI_DOMAIN 3
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- #power-domain-cells: Should be 0
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Optional properties:
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- clocks: a number of phandles to clocks that need to be enabled during domain
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power-up sequencing to ensure reset propagation into devices located inside
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this power domain
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- power-supply: a phandle to the regulator powering this domain
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Example:
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gpc: gpc@20dc000 {
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compatible = "fsl,imx6q-gpc";
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reg = <0x020dc000 0x4000>;
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interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
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<0 90 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX6QDL_CLK_IPG>;
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clock-names = "ipg";
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pgc {
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#address-cells = <1>;
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#size-cells = <0>;
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power-domain@0 {
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reg = <0>;
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#power-domain-cells = <0>;
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};
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pd_pu: power-domain@1 {
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reg = <1>;
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#power-domain-cells = <0>;
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power-supply = <®_pu>;
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clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,
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<&clks IMX6QDL_CLK_GPU3D_SHADER>,
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<&clks IMX6QDL_CLK_GPU2D_CORE>,
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<&clks IMX6QDL_CLK_GPU2D_AXI>,
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<&clks IMX6QDL_CLK_OPENVG_AXI>,
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<&clks IMX6QDL_CLK_VPU_AXI>;
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};
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};
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};
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Specifying power domain for IP modules
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======================================
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IP cores belonging to a power domain should contain a 'power-domains' property
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that is a phandle pointing to the power domain the device belongs to.
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Example of a device that is part of the PU power domain:
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vpu: vpu@2040000 {
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reg = <0x02040000 0x3c000>;
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/* ... */
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power-domains = <&pd_pu>;
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/* ... */
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};
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124
Documentation/devicetree/bindings/power/fsl,imx-gpc.yaml
Normal file
124
Documentation/devicetree/bindings/power/fsl,imx-gpc.yaml
Normal file
@ -0,0 +1,124 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/power/fsl,imx-gpc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Freescale i.MX General Power Controller
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maintainers:
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- Philipp Zabel <p.zabel@pengutronix.de>
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description: |
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The i.MX6 General Power Control (GPC) block contains DVFS load tracking
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counters and Power Gating Control (PGC).
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The power domains are generic power domain providers as documented in
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Documentation/devicetree/bindings/power/power-domain.yaml. They are
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described as subnodes of the power gating controller 'pgc' node of the GPC.
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IP cores belonging to a power domain should contain a 'power-domains'
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property that is a phandle pointing to the power domain the device belongs
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to.
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properties:
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compatible:
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enum:
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- fsl,imx6q-gpc
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- fsl,imx6qp-gpc
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- fsl,imx6sl-gpc
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- fsl,imx6sx-gpc
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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maxItems: 1
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clock-names:
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const: ipg
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pgc:
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type: object
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description: list of power domains provided by this controller.
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patternProperties:
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"power-domain@[0-9]$":
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type: object
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properties:
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'#power-domain-cells':
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const: 0
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reg:
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description: |
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The following DOMAIN_INDEX values are valid for i.MX6Q:
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ARM_DOMAIN 0
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PU_DOMAIN 1
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The following additional DOMAIN_INDEX value is valid for i.MX6SL:
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DISPLAY_DOMAIN 2
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The following additional DOMAIN_INDEX value is valid for i.MX6SX:
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PCI_DOMAIN 3
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maxItems: 1
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clocks:
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description: |
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A number of phandles to clocks that need to be enabled during domain
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power-up sequencing to ensure reset propagation into devices located
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inside this power domain.
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minItems: 1
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maxItems: 7
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power-supply: true
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required:
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- '#power-domain-cells'
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- reg
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- clock-names
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- pgc
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/imx6qdl-clock.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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gpc@20dc000 {
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compatible = "fsl,imx6q-gpc";
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reg = <0x020dc000 0x4000>;
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interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX6QDL_CLK_IPG>;
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clock-names = "ipg";
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pgc {
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#address-cells = <1>;
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#size-cells = <0>;
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power-domain@0 {
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reg = <0>;
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#power-domain-cells = <0>;
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};
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pd_pu: power-domain@1 {
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reg = <1>;
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#power-domain-cells = <0>;
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power-supply = <®_pu>;
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clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,
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<&clks IMX6QDL_CLK_GPU3D_SHADER>,
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<&clks IMX6QDL_CLK_GPU2D_CORE>,
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<&clks IMX6QDL_CLK_GPU2D_AXI>,
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<&clks IMX6QDL_CLK_OPENVG_AXI>,
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<&clks IMX6QDL_CLK_VPU_AXI>;
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};
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};
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};
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