forked from Minki/linux
powerpc/powernv/npu: Add compound IOMMU groups
At the moment the powernv platform registers an IOMMU group for each PE. There is an exception though: an NVLink bridge which is attached to the corresponding GPU's IOMMU group making it a master. Now we have POWER9 systems with GPUs connected to each other directly bypassing PCI. At the moment we do not control state of these links so we have to put such interconnected GPUs to one IOMMU group which means that the old scheme with one GPU as a master won't work - there will be up to 3 GPUs in such group. This introduces a npu_comp struct which represents a compound IOMMU group made of multiple PEs - PCI PEs (for GPUs) and NPU PEs (for NVLink bridges). This converts the existing NVLink1 code to use the new scheme. >From now on, each PE must have a valid iommu_table_group_ops which will either be called directly (for a single PE group) or indirectly from a compound group handlers. This moves IOMMU group registration for NVLink-connected GPUs to npu-dma.c. For POWER8, this stores a new compound group pointer in the PE (so a GPU is still a master); for POWER9 the new group pointer is stored in an NPU (which is allocated per a PCI host controller). Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> [mpe: Initialise npdev to NULL in pnv_try_setup_npu_table_group()] Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
This commit is contained in:
Alexey Kardashevskiy
Michael Ellerman
parent
83fb8ccf97
commit
0bd971676e
@ -132,5 +132,6 @@ extern struct pci_dev *pnv_pci_get_npu_dev(struct pci_dev *gpdev, int index);
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extern int pnv_npu2_init(struct pci_controller *hose);
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extern int pnv_npu2_map_lpar_dev(struct pci_dev *gpdev, unsigned int lparid,
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unsigned long msr);
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extern int pnv_npu2_unmap_lpar_dev(struct pci_dev *gpdev);
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#endif /* __ASM_POWERPC_PCI_H */
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@ -327,31 +327,6 @@ static struct iommu_table_group_ops pnv_pci_npu_ops = {
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.unset_window = pnv_npu_unset_window,
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.take_ownership = pnv_npu_take_ownership,
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};
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struct pnv_ioda_pe *pnv_pci_npu_setup_iommu(struct pnv_ioda_pe *npe)
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{
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struct pnv_phb *phb = npe->phb;
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struct pci_bus *pbus = phb->hose->bus;
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struct pci_dev *npdev, *gpdev = NULL, *gptmp;
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struct pnv_ioda_pe *gpe = get_gpu_pci_dev_and_pe(npe, &gpdev);
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if (!gpe || !gpdev)
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return NULL;
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npe->table_group.ops = &pnv_pci_npu_ops;
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list_for_each_entry(npdev, &pbus->devices, bus_list) {
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gptmp = pnv_pci_get_gpu_dev(npdev);
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if (gptmp != gpdev)
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continue;
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pe_info(gpe, "Attached NPU %s\n", dev_name(&npdev->dev));
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iommu_group_add_device(gpe->table_group.group, &npdev->dev);
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}
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return gpe;
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}
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#endif /* !CONFIG_IOMMU_API */
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/*
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@ -359,6 +334,17 @@ struct pnv_ioda_pe *pnv_pci_npu_setup_iommu(struct pnv_ioda_pe *npe)
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*/
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/* Maximum possible number of ATSD MMIO registers per NPU */
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#define NV_NMMU_ATSD_REGS 8
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#define NV_NPU_MAX_PE_NUM 16
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/*
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* A compound NPU IOMMU group which might consist of 1 GPU + 2xNPUs (POWER8) or
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* up to 3 x (GPU + 2xNPUs) (POWER9).
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*/
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struct npu_comp {
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struct iommu_table_group table_group;
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int pe_num;
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struct pnv_ioda_pe *pe[NV_NPU_MAX_PE_NUM];
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};
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/* An NPU descriptor, valid for POWER9 only */
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struct npu {
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@ -371,8 +357,263 @@ struct npu {
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/* Do we need to explicitly flush the nest mmu? */
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bool nmmu_flush;
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struct npu_comp npucomp;
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};
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#ifdef CONFIG_IOMMU_API
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static long pnv_npu_peers_create_table_userspace(
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struct iommu_table_group *table_group,
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int num, __u32 page_shift, __u64 window_size, __u32 levels,
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struct iommu_table **ptbl)
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{
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struct npu_comp *npucomp = container_of(table_group, struct npu_comp,
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table_group);
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if (!npucomp->pe_num || !npucomp->pe[0] ||
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!npucomp->pe[0]->table_group.ops ||
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!npucomp->pe[0]->table_group.ops->create_table)
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return -EFAULT;
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return npucomp->pe[0]->table_group.ops->create_table(
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&npucomp->pe[0]->table_group, num, page_shift,
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window_size, levels, ptbl);
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}
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static long pnv_npu_peers_set_window(struct iommu_table_group *table_group,
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int num, struct iommu_table *tbl)
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{
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int i, j;
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long ret = 0;
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struct npu_comp *npucomp = container_of(table_group, struct npu_comp,
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table_group);
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for (i = 0; i < npucomp->pe_num; ++i) {
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struct pnv_ioda_pe *pe = npucomp->pe[i];
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if (!pe->table_group.ops->set_window)
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continue;
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ret = pe->table_group.ops->set_window(&pe->table_group,
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num, tbl);
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if (ret)
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break;
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}
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if (ret) {
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for (j = 0; j < i; ++j) {
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struct pnv_ioda_pe *pe = npucomp->pe[j];
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if (!pe->table_group.ops->unset_window)
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continue;
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ret = pe->table_group.ops->unset_window(
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&pe->table_group, num);
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if (ret)
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break;
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}
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} else {
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table_group->tables[num] = iommu_tce_table_get(tbl);
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}
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return ret;
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}
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static long pnv_npu_peers_unset_window(struct iommu_table_group *table_group,
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int num)
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{
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int i, j;
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long ret = 0;
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struct npu_comp *npucomp = container_of(table_group, struct npu_comp,
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table_group);
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for (i = 0; i < npucomp->pe_num; ++i) {
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struct pnv_ioda_pe *pe = npucomp->pe[i];
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WARN_ON(npucomp->table_group.tables[num] !=
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table_group->tables[num]);
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if (!npucomp->table_group.tables[num])
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continue;
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if (!pe->table_group.ops->unset_window)
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continue;
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ret = pe->table_group.ops->unset_window(&pe->table_group, num);
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if (ret)
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break;
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}
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if (ret) {
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for (j = 0; j < i; ++j) {
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struct pnv_ioda_pe *pe = npucomp->pe[j];
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if (!npucomp->table_group.tables[num])
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continue;
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if (!pe->table_group.ops->set_window)
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continue;
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ret = pe->table_group.ops->set_window(&pe->table_group,
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num, table_group->tables[num]);
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if (ret)
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break;
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}
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} else if (table_group->tables[num]) {
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iommu_tce_table_put(table_group->tables[num]);
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table_group->tables[num] = NULL;
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}
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return ret;
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}
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static void pnv_npu_peers_take_ownership(struct iommu_table_group *table_group)
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{
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int i;
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struct npu_comp *npucomp = container_of(table_group, struct npu_comp,
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table_group);
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for (i = 0; i < npucomp->pe_num; ++i) {
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struct pnv_ioda_pe *pe = npucomp->pe[i];
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if (!pe->table_group.ops->take_ownership)
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continue;
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pe->table_group.ops->take_ownership(&pe->table_group);
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}
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}
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static void pnv_npu_peers_release_ownership(
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struct iommu_table_group *table_group)
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{
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int i;
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struct npu_comp *npucomp = container_of(table_group, struct npu_comp,
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table_group);
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for (i = 0; i < npucomp->pe_num; ++i) {
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struct pnv_ioda_pe *pe = npucomp->pe[i];
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if (!pe->table_group.ops->release_ownership)
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continue;
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pe->table_group.ops->release_ownership(&pe->table_group);
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}
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}
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static struct iommu_table_group_ops pnv_npu_peers_ops = {
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.get_table_size = pnv_pci_ioda2_get_table_size,
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.create_table = pnv_npu_peers_create_table_userspace,
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.set_window = pnv_npu_peers_set_window,
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.unset_window = pnv_npu_peers_unset_window,
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.take_ownership = pnv_npu_peers_take_ownership,
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.release_ownership = pnv_npu_peers_release_ownership,
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};
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static void pnv_comp_attach_table_group(struct npu_comp *npucomp,
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struct pnv_ioda_pe *pe)
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{
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if (WARN_ON(npucomp->pe_num == NV_NPU_MAX_PE_NUM))
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return;
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npucomp->pe[npucomp->pe_num] = pe;
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++npucomp->pe_num;
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}
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struct iommu_table_group *pnv_try_setup_npu_table_group(struct pnv_ioda_pe *pe)
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{
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struct iommu_table_group *table_group;
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struct npu_comp *npucomp;
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struct pci_dev *gpdev = NULL;
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struct pci_controller *hose;
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struct pci_dev *npdev = NULL;
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list_for_each_entry(gpdev, &pe->pbus->devices, bus_list) {
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npdev = pnv_pci_get_npu_dev(gpdev, 0);
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if (npdev)
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break;
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}
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if (!npdev)
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/* It is not an NPU attached device, skip */
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return NULL;
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hose = pci_bus_to_host(npdev->bus);
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if (hose->npu) {
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table_group = &hose->npu->npucomp.table_group;
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if (!table_group->group) {
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table_group->ops = &pnv_npu_peers_ops;
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iommu_register_group(table_group,
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hose->global_number,
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pe->pe_number);
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}
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} else {
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/* Create a group for 1 GPU and attached NPUs for POWER8 */
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pe->npucomp = kzalloc(sizeof(pe->npucomp), GFP_KERNEL);
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table_group = &pe->npucomp->table_group;
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table_group->ops = &pnv_npu_peers_ops;
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iommu_register_group(table_group, hose->global_number,
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pe->pe_number);
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}
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/* Steal capabilities from a GPU PE */
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table_group->max_dynamic_windows_supported =
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pe->table_group.max_dynamic_windows_supported;
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table_group->tce32_start = pe->table_group.tce32_start;
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table_group->tce32_size = pe->table_group.tce32_size;
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table_group->max_levels = pe->table_group.max_levels;
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if (!table_group->pgsizes)
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table_group->pgsizes = pe->table_group.pgsizes;
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npucomp = container_of(table_group, struct npu_comp, table_group);
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pnv_comp_attach_table_group(npucomp, pe);
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return table_group;
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}
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struct iommu_table_group *pnv_npu_compound_attach(struct pnv_ioda_pe *pe)
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{
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struct iommu_table_group *table_group;
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struct npu_comp *npucomp;
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struct pci_dev *gpdev = NULL;
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struct pci_dev *npdev;
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struct pnv_ioda_pe *gpe = get_gpu_pci_dev_and_pe(pe, &gpdev);
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WARN_ON(!(pe->flags & PNV_IODA_PE_DEV));
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if (!gpe)
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return NULL;
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/*
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* IODA2 bridges get this set up from pci_controller_ops::setup_bridge
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* but NPU bridges do not have this hook defined so we do it here.
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* We do not setup other table group parameters as they won't be used
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* anyway - NVLink bridges are subordinate PEs.
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*/
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pe->table_group.ops = &pnv_pci_npu_ops;
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table_group = iommu_group_get_iommudata(
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iommu_group_get(&gpdev->dev));
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/*
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* On P9 NPU PHB and PCI PHB support different page sizes,
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* keep only matching. We expect here that NVLink bridge PE pgsizes is
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* initialized by the caller.
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*/
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table_group->pgsizes &= pe->table_group.pgsizes;
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npucomp = container_of(table_group, struct npu_comp, table_group);
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pnv_comp_attach_table_group(npucomp, pe);
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list_for_each_entry(npdev, &pe->phb->hose->bus->devices, bus_list) {
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struct pci_dev *gpdevtmp = pnv_pci_get_gpu_dev(npdev);
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if (gpdevtmp != gpdev)
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continue;
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iommu_add_device(table_group, &npdev->dev);
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}
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return table_group;
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}
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#endif /* CONFIG_IOMMU_API */
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/* Maximum number of nvlinks per npu */
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#define NV_MAX_LINKS 6
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@ -190,7 +190,8 @@ static void pnv_ioda_free_pe(struct pnv_ioda_pe *pe)
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unsigned int pe_num = pe->pe_number;
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WARN_ON(pe->pdev);
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WARN_ON(pe->npucomp); /* NPUs are not supposed to be freed */
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kfree(pe->npucomp);
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memset(pe, 0, sizeof(struct pnv_ioda_pe));
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clear_bit(pe_num, phb->ioda.pe_alloc);
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}
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@ -1534,7 +1535,9 @@ void pnv_pci_sriov_disable(struct pci_dev *pdev)
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static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
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struct pnv_ioda_pe *pe);
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#ifdef CONFIG_IOMMU_API
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static void pnv_ioda_setup_bus_iommu_group(struct pnv_ioda_pe *pe);
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static void pnv_ioda_setup_bus_iommu_group(struct pnv_ioda_pe *pe,
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struct iommu_table_group *table_group, struct pci_bus *bus);
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#endif
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static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs)
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{
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@ -1590,7 +1593,7 @@ static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs)
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pnv_pci_ioda2_setup_dma_pe(phb, pe);
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#ifdef CONFIG_IOMMU_API
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pnv_ioda_setup_bus_iommu_group(pe);
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pnv_ioda_setup_bus_iommu_group(pe, &pe->table_group, NULL);
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#endif
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}
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}
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@ -2552,7 +2555,7 @@ static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group,
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#endif
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#ifdef CONFIG_IOMMU_API
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static unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift,
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unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift,
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__u64 window_size, __u32 levels)
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{
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unsigned long bytes = 0;
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@ -2626,127 +2629,40 @@ static struct iommu_table_group_ops pnv_pci_ioda2_ops = {
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.release_ownership = pnv_ioda2_release_ownership,
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};
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static int gpe_table_group_to_npe_cb(struct device *dev, void *opaque)
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{
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struct pci_controller *hose;
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struct pnv_phb *phb;
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struct pnv_ioda_pe **ptmppe = opaque;
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struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
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struct pci_dn *pdn = pci_get_pdn(pdev);
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if (!pdn || pdn->pe_number == IODA_INVALID_PE)
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return 0;
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hose = pci_bus_to_host(pdev->bus);
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phb = hose->private_data;
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if (phb->type != PNV_PHB_NPU_NVLINK)
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return 0;
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*ptmppe = &phb->ioda.pe_array[pdn->pe_number];
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return 1;
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}
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/*
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* This returns PE of associated NPU.
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* This assumes that NPU is in the same IOMMU group with GPU and there is
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* no other PEs.
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*/
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static struct pnv_ioda_pe *gpe_table_group_to_npe(
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struct iommu_table_group *table_group)
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{
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struct pnv_ioda_pe *npe = NULL;
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int ret = iommu_group_for_each_dev(table_group->group, &npe,
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gpe_table_group_to_npe_cb);
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BUG_ON(!ret || !npe);
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return npe;
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}
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static long pnv_pci_ioda2_npu_set_window(struct iommu_table_group *table_group,
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int num, struct iommu_table *tbl)
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{
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struct pnv_ioda_pe *npe = gpe_table_group_to_npe(table_group);
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long ret = pnv_pci_ioda2_set_window(table_group, num, tbl);
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if (ret)
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return ret;
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ret = npe->table_group.ops->set_window(&npe->table_group, num, tbl);
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if (ret)
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pnv_pci_ioda2_unset_window(table_group, num);
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return ret;
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}
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||||
|
||||
static long pnv_pci_ioda2_npu_unset_window(
|
||||
struct iommu_table_group *table_group,
|
||||
int num)
|
||||
{
|
||||
struct pnv_ioda_pe *npe = gpe_table_group_to_npe(table_group);
|
||||
long ret = pnv_pci_ioda2_unset_window(table_group, num);
|
||||
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return npe->table_group.ops->unset_window(&npe->table_group, num);
|
||||
}
|
||||
|
||||
static void pnv_ioda2_npu_take_ownership(struct iommu_table_group *table_group)
|
||||
{
|
||||
struct pnv_ioda_pe *npe = gpe_table_group_to_npe(table_group);
|
||||
|
||||
npe->table_group.ops->take_ownership(&npe->table_group);
|
||||
pnv_ioda2_take_ownership(table_group);
|
||||
}
|
||||
|
||||
static struct iommu_table_group_ops pnv_pci_ioda2_npu_ops = {
|
||||
.get_table_size = pnv_pci_ioda2_get_table_size,
|
||||
.create_table = pnv_pci_ioda2_create_table_userspace,
|
||||
.set_window = pnv_pci_ioda2_npu_set_window,
|
||||
.unset_window = pnv_pci_ioda2_npu_unset_window,
|
||||
.take_ownership = pnv_ioda2_npu_take_ownership,
|
||||
.release_ownership = pnv_ioda2_release_ownership,
|
||||
};
|
||||
|
||||
static void pnv_ioda_setup_bus_iommu_group_add_devices(struct pnv_ioda_pe *pe,
|
||||
struct iommu_table_group *table_group,
|
||||
struct pci_bus *bus)
|
||||
{
|
||||
struct pci_dev *dev;
|
||||
|
||||
list_for_each_entry(dev, &bus->devices, bus_list) {
|
||||
iommu_add_device(&pe->table_group, &dev->dev);
|
||||
iommu_add_device(table_group, &dev->dev);
|
||||
|
||||
if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
|
||||
pnv_ioda_setup_bus_iommu_group_add_devices(pe,
|
||||
dev->subordinate);
|
||||
table_group, dev->subordinate);
|
||||
}
|
||||
}
|
||||
|
||||
static void pnv_ioda_setup_bus_iommu_group(struct pnv_ioda_pe *pe)
|
||||
static void pnv_ioda_setup_bus_iommu_group(struct pnv_ioda_pe *pe,
|
||||
struct iommu_table_group *table_group, struct pci_bus *bus)
|
||||
{
|
||||
if (!pnv_pci_ioda_pe_dma_weight(pe))
|
||||
return;
|
||||
|
||||
iommu_register_group(&pe->table_group, pe->phb->hose->global_number,
|
||||
pe->pe_number);
|
||||
|
||||
/*
|
||||
* set_iommu_table_base(&pe->pdev->dev, tbl) should have been called
|
||||
* by now
|
||||
*/
|
||||
if (pe->flags & PNV_IODA_PE_DEV)
|
||||
iommu_add_device(&pe->table_group, &pe->pdev->dev);
|
||||
else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
|
||||
pnv_ioda_setup_bus_iommu_group_add_devices(pe, pe->pbus);
|
||||
iommu_add_device(table_group, &pe->pdev->dev);
|
||||
|
||||
if ((pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) || bus)
|
||||
pnv_ioda_setup_bus_iommu_group_add_devices(pe, table_group,
|
||||
bus);
|
||||
}
|
||||
|
||||
static unsigned long pnv_ioda_parse_tce_sizes(struct pnv_phb *phb);
|
||||
|
||||
static void pnv_pci_ioda_setup_iommu_api(void)
|
||||
{
|
||||
struct pci_controller *hose, *tmp;
|
||||
struct pci_controller *hose;
|
||||
struct pnv_phb *phb;
|
||||
struct pnv_ioda_pe *pe, *gpe;
|
||||
struct pnv_ioda_pe *pe;
|
||||
|
||||
/*
|
||||
* There are 4 types of PEs:
|
||||
@ -2768,24 +2684,45 @@ static void pnv_pci_ioda_setup_iommu_api(void)
|
||||
if (phb->type == PNV_PHB_NPU_NVLINK)
|
||||
continue;
|
||||
|
||||
list_for_each_entry(pe, &phb->ioda.pe_list, list)
|
||||
pnv_ioda_setup_bus_iommu_group(pe);
|
||||
list_for_each_entry(pe, &phb->ioda.pe_list, list) {
|
||||
struct iommu_table_group *table_group;
|
||||
|
||||
table_group = pnv_try_setup_npu_table_group(pe);
|
||||
if (!table_group) {
|
||||
if (!pnv_pci_ioda_pe_dma_weight(pe))
|
||||
continue;
|
||||
|
||||
table_group = &pe->table_group;
|
||||
iommu_register_group(&pe->table_group,
|
||||
pe->phb->hose->global_number,
|
||||
pe->pe_number);
|
||||
}
|
||||
pnv_ioda_setup_bus_iommu_group(pe, table_group,
|
||||
pe->pbus);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Now we have all PHBs discovered, time to add NPU devices to
|
||||
* the corresponding IOMMU groups.
|
||||
*/
|
||||
list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
|
||||
list_for_each_entry(hose, &hose_list, list_node) {
|
||||
unsigned long pgsizes;
|
||||
|
||||
phb = hose->private_data;
|
||||
|
||||
if (phb->type != PNV_PHB_NPU_NVLINK)
|
||||
continue;
|
||||
|
||||
pgsizes = pnv_ioda_parse_tce_sizes(phb);
|
||||
list_for_each_entry(pe, &phb->ioda.pe_list, list) {
|
||||
gpe = pnv_pci_npu_setup_iommu(pe);
|
||||
if (gpe)
|
||||
gpe->table_group.ops = &pnv_pci_ioda2_npu_ops;
|
||||
/*
|
||||
* IODA2 bridges get this set up from
|
||||
* pci_controller_ops::setup_bridge but NPU bridges
|
||||
* do not have this hook defined so we do it here.
|
||||
*/
|
||||
pe->table_group.pgsizes = pgsizes;
|
||||
pnv_npu_compound_attach(pe);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@ -62,6 +62,7 @@ struct pnv_ioda_pe {
|
||||
|
||||
/* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */
|
||||
struct iommu_table_group table_group;
|
||||
struct npu_comp *npucomp;
|
||||
|
||||
/* 64-bit TCE bypass region */
|
||||
bool tce_bypass_enabled;
|
||||
@ -199,6 +200,8 @@ extern void pnv_teardown_msi_irqs(struct pci_dev *pdev);
|
||||
extern struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev);
|
||||
extern void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq);
|
||||
extern void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable);
|
||||
extern unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift,
|
||||
__u64 window_size, __u32 levels);
|
||||
extern int pnv_eeh_post_init(void);
|
||||
|
||||
extern void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level,
|
||||
@ -214,6 +217,10 @@ extern void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level,
|
||||
extern void pnv_npu_try_dma_set_bypass(struct pci_dev *gpdev, bool bypass);
|
||||
extern void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb *phb, bool rm);
|
||||
extern struct pnv_ioda_pe *pnv_pci_npu_setup_iommu(struct pnv_ioda_pe *npe);
|
||||
extern struct iommu_table_group *pnv_try_setup_npu_table_group(
|
||||
struct pnv_ioda_pe *pe);
|
||||
extern struct iommu_table_group *pnv_npu_compound_attach(
|
||||
struct pnv_ioda_pe *pe);
|
||||
|
||||
/* pci-ioda-tce.c */
|
||||
#define POWERNV_IOMMU_DEFAULT_LEVELS 1
|
||||
|
||||
Loading…
Reference in New Issue
Block a user