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i40e/i40evf: unhide and enable to one prefena field

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The PREFENA field in the receive host memory cache (RX-HMC)
must be visible in order to be set to 1 at driver init for
best performance.

Change-ID: I16b0bcd84cf56f4b6c938201ff5e954bee5a1992
Signed-off-by: Jesse Brandeburg <jesse.brandeburg@intel.com>
Acked-by: Shannon Nelson <shannon.nelson@intel.com>
Tested-by: Kavindya Deegala <kavindya.s.deegala@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
This commit is contained in:
Jesse Brandeburg 2014-03-06 09:02:27 +00:00 committed by Jeff Kirsher
parent 4ba0dea5b1
commit 0b3aec852b
4 changed files with 5 additions and 0 deletions
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1
drivers/net/ethernet/intel/i40e/i40e_lan_hmc.c
View File

@ -747,6 +747,7 @@ static struct i40e_context_ele i40e_hmc_rxq_ce_info[] = {
{ I40E_HMC_STORE(i40e_hmc_obj_rxq, tphdata_ena), 1, 195 }, { I40E_HMC_STORE(i40e_hmc_obj_rxq, tphdata_ena), 1, 195 },
{ I40E_HMC_STORE(i40e_hmc_obj_rxq, tphhead_ena), 1, 196 }, { I40E_HMC_STORE(i40e_hmc_obj_rxq, tphhead_ena), 1, 196 },
{ I40E_HMC_STORE(i40e_hmc_obj_rxq, lrxqthresh), 3, 198 }, { I40E_HMC_STORE(i40e_hmc_obj_rxq, lrxqthresh), 3, 198 },
{ I40E_HMC_STORE(i40e_hmc_obj_rxq, prefena), 1, 201 },
{ 0 } { 0 }
}; };

1
drivers/net/ethernet/intel/i40e/i40e_lan_hmc.h
View File

@ -56,6 +56,7 @@ struct i40e_hmc_obj_rxq {
u8 tphdata_ena; u8 tphdata_ena;
u8 tphhead_ena; u8 tphhead_ena;
u8 lrxqthresh; u8 lrxqthresh;
u8 prefena; /* NOTE: normally must be set to 1 at init */
}; };
/* Tx queue context data */ /* Tx queue context data */

2
drivers/net/ethernet/intel/i40e/i40e_main.c
View File

@ -3140,6 +3140,8 @@ static void i40e_netpoll(struct net_device *netdev)
pf->flags &= ~I40E_FLAG_IN_NETPOLL; pf->flags &= ~I40E_FLAG_IN_NETPOLL;
} }
#endif #endif
/* set the prefena field to 1 because the manual says to */
rx_ctx.prefena = 1;
/** /**
* i40e_vsi_control_tx - Start or stop a VSI's rings * i40e_vsi_control_tx - Start or stop a VSI's rings

1
drivers/net/ethernet/intel/i40evf/i40e_lan_hmc.h
View File

@ -53,6 +53,7 @@ struct i40e_hmc_obj_rxq {
u8 tphdata_ena; u8 tphdata_ena;
u8 tphhead_ena; u8 tphhead_ena;
u8 lrxqthresh; u8 lrxqthresh;
u8 prefena; /* NOTE: normally must be set to 1 at init */
}; };
/* Tx queue context data */ /* Tx queue context data */