forked from Minki/linux
tools/power turbostat: Initial Skylake support
Skylake adds some additional residency counters. Skylake supports a different mix of RAPL registers from any previous product. In most other ways, Skylake is like Broadwell. Signed-off-by: Len Brown <len.brown@intel.com>
This commit is contained in:
Len Brown
parent
f82263c698
commit
0b2bb6925e
@ -150,6 +150,11 @@
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#define MSR_PP1_ENERGY_STATUS 0x00000641
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#define MSR_PP1_POLICY 0x00000642
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#define MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658
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#define MSR_PKG_ANY_CORE_C0_RES 0x00000659
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#define MSR_PKG_ANY_GFXE_C0_RES 0x0000065A
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#define MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B
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#define MSR_CORE_C1_RES 0x00000660
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#define MSR_CC6_DEMOTION_POLICY_CONFIG 0x00000668
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@ -57,6 +57,7 @@ unsigned int do_pc3;
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unsigned int do_pc6;
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unsigned int do_pc7;
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unsigned int do_c8_c9_c10;
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unsigned int do_skl_residency;
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unsigned int do_slm_cstates;
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unsigned int use_c1_residency_msr;
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unsigned int has_aperf;
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@ -99,18 +100,18 @@ unsigned int do_ring_perf_limit_reasons;
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#define RAPL_DRAM (1 << 3)
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/* 0x618 MSR_DRAM_POWER_LIMIT */
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/* 0x619 MSR_DRAM_ENERGY_STATUS */
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/* 0x61c MSR_DRAM_POWER_INFO */
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#define RAPL_DRAM_PERF_STATUS (1 << 4)
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/* 0x61b MSR_DRAM_PERF_STATUS */
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#define RAPL_DRAM_POWER_INFO (1 << 5)
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/* 0x61c MSR_DRAM_POWER_INFO */
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#define RAPL_CORES (1 << 5)
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#define RAPL_CORES (1 << 6)
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/* 0x638 MSR_PP0_POWER_LIMIT */
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/* 0x639 MSR_PP0_ENERGY_STATUS */
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#define RAPL_CORE_POLICY (1 << 6)
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#define RAPL_CORE_POLICY (1 << 7)
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/* 0x63a MSR_PP0_POLICY */
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#define RAPL_GFX (1 << 7)
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#define RAPL_GFX (1 << 8)
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/* 0x640 MSR_PP1_POWER_LIMIT */
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/* 0x641 MSR_PP1_ENERGY_STATUS */
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/* 0x642 MSR_PP1_POLICY */
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@ -157,6 +158,10 @@ struct pkg_data {
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unsigned long long pc8;
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unsigned long long pc9;
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unsigned long long pc10;
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unsigned long long pkg_wtd_core_c0;
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unsigned long long pkg_any_core_c0;
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unsigned long long pkg_any_gfxe_c0;
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unsigned long long pkg_both_core_gfxe_c0;
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unsigned int package_id;
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unsigned int energy_pkg; /* MSR_PKG_ENERGY_STATUS */
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unsigned int energy_dram; /* MSR_DRAM_ENERGY_STATUS */
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@ -320,6 +325,13 @@ void print_header(void)
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if (do_ptm)
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outp += sprintf(outp, " PkgTmp");
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if (do_skl_residency) {
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outp += sprintf(outp, " Totl%%C0");
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outp += sprintf(outp, " Any%%C0");
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outp += sprintf(outp, " GFX%%C0");
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outp += sprintf(outp, " CPUGFX%%");
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}
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if (do_pc2)
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outp += sprintf(outp, " Pkg%%pc2");
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if (do_pc3)
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@ -401,6 +413,12 @@ int dump_counters(struct thread_data *t, struct core_data *c,
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if (p) {
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outp += sprintf(outp, "package: %d\n", p->package_id);
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outp += sprintf(outp, "Weighted cores: %016llX\n", p->pkg_wtd_core_c0);
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outp += sprintf(outp, "Any cores: %016llX\n", p->pkg_any_core_c0);
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outp += sprintf(outp, "Any GFX: %016llX\n", p->pkg_any_gfxe_c0);
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outp += sprintf(outp, "CPU + GFX: %016llX\n", p->pkg_both_core_gfxe_c0);
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outp += sprintf(outp, "pc2: %016llX\n", p->pc2);
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if (do_pc3)
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outp += sprintf(outp, "pc3: %016llX\n", p->pc3);
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@ -539,9 +557,18 @@ int format_counters(struct thread_data *t, struct core_data *c,
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if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
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goto done;
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/* PkgTmp */
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if (do_ptm)
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outp += sprintf(outp, "%8d", p->pkg_temp_c);
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/* Totl%C0, Any%C0 GFX%C0 CPUGFX% */
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if (do_skl_residency) {
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outp += sprintf(outp, "%8.2f", 100.0 * p->pkg_wtd_core_c0/t->tsc);
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outp += sprintf(outp, "%8.2f", 100.0 * p->pkg_any_core_c0/t->tsc);
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outp += sprintf(outp, "%8.2f", 100.0 * p->pkg_any_gfxe_c0/t->tsc);
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outp += sprintf(outp, "%8.2f", 100.0 * p->pkg_both_core_gfxe_c0/t->tsc);
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}
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if (do_pc2)
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outp += sprintf(outp, "%8.2f", 100.0 * p->pc2/t->tsc);
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if (do_pc3)
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@ -644,6 +671,13 @@ void format_all_counters(struct thread_data *t, struct core_data *c, struct pkg_
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void
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delta_package(struct pkg_data *new, struct pkg_data *old)
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{
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if (do_skl_residency) {
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old->pkg_wtd_core_c0 = new->pkg_wtd_core_c0 - old->pkg_wtd_core_c0;
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old->pkg_any_core_c0 = new->pkg_any_core_c0 - old->pkg_any_core_c0;
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old->pkg_any_gfxe_c0 = new->pkg_any_gfxe_c0 - old->pkg_any_gfxe_c0;
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old->pkg_both_core_gfxe_c0 = new->pkg_both_core_gfxe_c0 - old->pkg_both_core_gfxe_c0;
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}
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old->pc2 = new->pc2 - old->pc2;
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if (do_pc3)
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old->pc3 = new->pc3 - old->pc3;
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@ -790,6 +824,11 @@ void clear_counters(struct thread_data *t, struct core_data *c, struct pkg_data
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c->c7 = 0;
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c->core_temp_c = 0;
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p->pkg_wtd_core_c0 = 0;
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p->pkg_any_core_c0 = 0;
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p->pkg_any_gfxe_c0 = 0;
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p->pkg_both_core_gfxe_c0 = 0;
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p->pc2 = 0;
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if (do_pc3)
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p->pc3 = 0;
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@ -834,6 +873,13 @@ int sum_counters(struct thread_data *t, struct core_data *c,
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if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
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return 0;
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if (do_skl_residency) {
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average.packages.pkg_wtd_core_c0 += p->pkg_wtd_core_c0;
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average.packages.pkg_any_core_c0 += p->pkg_any_core_c0;
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average.packages.pkg_any_gfxe_c0 += p->pkg_any_gfxe_c0;
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average.packages.pkg_both_core_gfxe_c0 += p->pkg_both_core_gfxe_c0;
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}
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average.packages.pc2 += p->pc2;
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if (do_pc3)
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average.packages.pc3 += p->pc3;
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@ -881,6 +927,13 @@ void compute_average(struct thread_data *t, struct core_data *c,
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average.cores.c6 /= topo.num_cores;
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average.cores.c7 /= topo.num_cores;
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if (do_skl_residency) {
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average.packages.pkg_wtd_core_c0 /= topo.num_packages;
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average.packages.pkg_any_core_c0 /= topo.num_packages;
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average.packages.pkg_any_gfxe_c0 /= topo.num_packages;
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average.packages.pkg_both_core_gfxe_c0 /= topo.num_packages;
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}
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average.packages.pc2 /= topo.num_packages;
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if (do_pc3)
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average.packages.pc3 /= topo.num_packages;
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@ -987,6 +1040,16 @@ int get_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p)
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if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
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return 0;
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if (do_skl_residency) {
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if (get_msr(cpu, MSR_PKG_WEIGHTED_CORE_C0_RES, &p->pkg_wtd_core_c0))
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return -10;
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if (get_msr(cpu, MSR_PKG_ANY_CORE_C0_RES, &p->pkg_any_core_c0))
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return -11;
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if (get_msr(cpu, MSR_PKG_ANY_GFXE_C0_RES, &p->pkg_any_gfxe_c0))
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return -12;
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if (get_msr(cpu, MSR_PKG_BOTH_CORE_GFXE_C0_RES, &p->pkg_both_core_gfxe_c0))
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return -13;
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}
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if (do_pc3)
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if (get_msr(cpu, MSR_PKG_C3_RESIDENCY, &p->pc3))
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return -9;
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@ -1063,15 +1126,18 @@ int get_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p)
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#define PCL_6R 9 /* PC6 Retention */
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#define PCL__7 10 /* PC7 */
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#define PCL_7S 11 /* PC7 Shrink */
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#define PCLUNL 12 /* Unlimited */
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#define PCL__8 12 /* PC8 */
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#define PCL__9 13 /* PC9 */
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#define PCLUNL 14 /* Unlimited */
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int pkg_cstate_limit = PCLUKN;
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char *pkg_cstate_limit_strings[] = { "reserved", "unknown", "pc0", "pc1", "pc2",
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"pc3", "pc4", "pc6", "pc6n", "pc6r", "pc7", "pc7s", "unlimited"};
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"pc3", "pc4", "pc6", "pc6n", "pc6r", "pc7", "pc7s", "pc8", "pc9", "unlimited"};
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int nhm_pkg_cstate_limits[8] = {PCL__0, PCL__1, PCL__3, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLUNL};
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int snb_pkg_cstate_limits[8] = {PCL__0, PCL__2, PCL_6N, PCL_6R, PCL__7, PCL_7S, PCLRSV, PCLUNL};
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int hsw_pkg_cstate_limits[8] = {PCL__0, PCL__2, PCL__3, PCL__6, PCL__7, PCL_7S, PCLRSV, PCLUNL};
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int skl_pkg_cstate_limits[8] = {PCL__0, PCL__2, PCL__3, PCL__6, PCL__7, PCL_7S, PCL__8, PCL__9};
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int slv_pkg_cstate_limits[8] = {PCL__0, PCL__1, PCLRSV, PCLRSV, PCL__4, PCLRSV, PCL__6, PCL__7};
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int amt_pkg_cstate_limits[8] = {PCL__0, PCL__1, PCL__2, PCLRSV, PCLRSV, PCLRSV, PCL__6, PCL__7};
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int phi_pkg_cstate_limits[8] = {PCL__0, PCL__2, PCL_6N, PCL_6R, PCLRSV, PCLRSV, PCLRSV, PCLUNL};
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@ -1619,6 +1685,8 @@ int probe_nhm_msrs(unsigned int family, unsigned int model)
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case 0x47: /* BDW */
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case 0x4F: /* BDX */
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case 0x56: /* BDX-DE */
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case 0x4E: /* SKL */
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case 0x5E: /* SKL */
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pkg_cstate_limits = hsw_pkg_cstate_limits;
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break;
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case 0x37: /* BYT */
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@ -1895,14 +1963,18 @@ void rapl_probe(unsigned int family, unsigned int model)
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case 0x47: /* BDW */
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do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_GFX | RAPL_PKG_POWER_INFO;
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break;
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case 0x4E: /* SKL */
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case 0x5E: /* SKL */
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do_rapl = RAPL_PKG | RAPL_DRAM | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO;
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break;
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case 0x3F: /* HSX */
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case 0x4F: /* BDX */
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case 0x56: /* BDX-DE */
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do_rapl = RAPL_PKG | RAPL_DRAM | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO;
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do_rapl = RAPL_PKG | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO;
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break;
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case 0x2D:
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case 0x3E:
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do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_DRAM | RAPL_PKG_PERF_STATUS | RAPL_DRAM_PERF_STATUS | RAPL_PKG_POWER_INFO;
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do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_PKG_PERF_STATUS | RAPL_DRAM_PERF_STATUS | RAPL_PKG_POWER_INFO;
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break;
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case 0x37: /* BYT */
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case 0x4D: /* AVN */
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@ -2092,19 +2164,18 @@ int print_rapl(struct thread_data *t, struct core_data *c, struct pkg_data *p)
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((msr >> 48) & 1) ? "EN" : "DIS");
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}
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if (do_rapl & RAPL_DRAM) {
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if (do_rapl & RAPL_DRAM_POWER_INFO) {
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if (get_msr(cpu, MSR_DRAM_POWER_INFO, &msr))
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return -6;
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fprintf(stderr, "cpu%d: MSR_DRAM_POWER_INFO,: 0x%08llx (%.0f W TDP, RAPL %.0f - %.0f W, %f sec.)\n",
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cpu, msr,
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((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units,
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((msr >> 16) & RAPL_POWER_GRANULARITY) * rapl_power_units,
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((msr >> 32) & RAPL_POWER_GRANULARITY) * rapl_power_units,
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((msr >> 48) & RAPL_TIME_GRANULARITY) * rapl_time_units);
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}
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if (do_rapl & RAPL_DRAM) {
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if (get_msr(cpu, MSR_DRAM_POWER_LIMIT, &msr))
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return -9;
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fprintf(stderr, "cpu%d: MSR_DRAM_POWER_LIMIT: 0x%08llx (%slocked)\n",
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@ -2173,6 +2244,8 @@ int has_snb_msrs(unsigned int family, unsigned int model)
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case 0x47: /* BDW */
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case 0x4F: /* BDX */
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case 0x56: /* BDX-DE */
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case 0x4E: /* SKL */
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case 0x5E: /* SKL */
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return 1;
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}
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return 0;
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@ -2193,11 +2266,35 @@ int has_hsw_msrs(unsigned int family, unsigned int model)
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switch (model) {
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case 0x45: /* HSW */
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case 0x3D: /* BDW */
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case 0x4E: /* SKL */
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case 0x5E: /* SKL */
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return 1;
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}
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return 0;
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}
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/*
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* SKL adds support for additional MSRS:
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*
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* MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658
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* MSR_PKG_ANY_CORE_C0_RES 0x00000659
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* MSR_PKG_ANY_GFXE_C0_RES 0x0000065A
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* MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B
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*/
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int has_skl_msrs(unsigned int family, unsigned int model)
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{
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if (!genuine_intel)
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return 0;
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switch (model) {
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case 0x4E: /* SKL */
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case 0x5E: /* SKL */
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return 1;
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}
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return 0;
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}
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int is_slm(unsigned int family, unsigned int model)
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{
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@ -2384,6 +2481,7 @@ void process_cpuid()
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do_pc6 = (pkg_cstate_limit >= PCL__6);
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do_pc7 = do_snb_cstates && (pkg_cstate_limit >= PCL__7);
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do_c8_c9_c10 = has_hsw_msrs(family, model);
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do_skl_residency = has_skl_msrs(family, model);
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do_slm_cstates = is_slm(family, model);
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bclk = discover_bclk(family, model);
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