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Merge branches 'rmobile/ag5' and 'rmobile/mmcif' into rmobile-latest

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This commit is contained in:
Paul Mundt 2010-11-30 14:50:10 +09:00
commit 0ae26c8cf7
6 changed files with 66 additions and 26 deletions
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41
arch/arm/mach-shmobile/board-ag5evm.c
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@ -33,6 +33,8 @@
#include <linux/input.h>
#include <linux/input/sh_keysc.h>
#include <sound/sh_fsi.h>
#include <mach/hardware.h>
#include <mach/sh73a0.h>
#include <mach/common.h>
@ -113,9 +115,41 @@ static struct platform_device keysc_device = {
},
};
/* FSI A */
static struct sh_fsi_platform_info fsi_info = {
.porta_flags = SH_FSI_OUT_SLAVE_MODE |
SH_FSI_IN_SLAVE_MODE |
SH_FSI_OFMT(I2S) |
SH_FSI_IFMT(I2S),
};
static struct resource fsi_resources[] = {
[0] = {
.name = "FSI",
.start = 0xEC230000,
.end = 0xEC230400 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = gic_spi(146),
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device fsi_device = {
.name = "sh_fsi2",
.id = -1,
.num_resources = ARRAY_SIZE(fsi_resources),
.resource = fsi_resources,
.dev = {
.platform_data = &fsi_info,
},
};
static struct platform_device *ag5evm_devices[] __initdata = {
&eth_device,
&keysc_device,
&fsi_device,
};
static struct map_desc ag5evm_io_desc[] __initdata = {
@ -195,6 +229,13 @@ static void __init ag5evm_init(void)
gpio_request(GPIO_PORT145, NULL); /* RESET */
gpio_direction_output(GPIO_PORT145, 1);
/* FSI A */
gpio_request(GPIO_FN_FSIACK, NULL);
gpio_request(GPIO_FN_FSIAILR, NULL);
gpio_request(GPIO_FN_FSIAIBT, NULL);
gpio_request(GPIO_FN_FSIAISLD, NULL);
gpio_request(GPIO_FN_FSIAOSLD, NULL);
#ifdef CONFIG_CACHE_L2X0
/* Shared attribute override enable, 64K*8way */
l2x0_init(__io(0xf0100000), 0x00460000, 0xc2000fff);

19
arch/arm/mach-shmobile/clock-sh73a0.c
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@ -51,10 +51,11 @@ static struct clk *main_clks[] = {
&hp_clk,
};
enum { MSTP219,
MSTP001, MSTP116, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202,
MSTP201, MSTP200, MSTP323, MSTP331, MSTP329, MSTP312, MSTP411,
MSTP410, MSTP403,
enum { MSTP001,
MSTP116,
MSTP219, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
MSTP331, MSTP329, MSTP323,
MSTP411, MSTP410, MSTP403,
MSTP_NR };
#define MSTP(_parent, _reg, _bit, _flags) \
@ -62,8 +63,8 @@ enum { MSTP219,
static struct clk mstp_clks[MSTP_NR] = {
[MSTP001] = MSTP(&hp_clk, SMSTPCR0, 1, 0), /* I2C2 */
[MSTP219] = MSTP(&sub_clk, SMSTPCR2, 19, 0), /* SCIFA7 */
[MSTP116] = MSTP(&hp_clk, SMSTPCR1, 16, 0), /* I2C0 */
[MSTP219] = MSTP(&sub_clk, SMSTPCR2, 19, 0), /* SCIFA7 */
[MSTP207] = MSTP(&sub_clk, SMSTPCR2, 7, 0), /* SCIFA5 */
[MSTP206] = MSTP(&sub_clk, SMSTPCR2, 6, 0), /* SCIFB */
[MSTP204] = MSTP(&sub_clk, SMSTPCR2, 4, 0), /* SCIFA0 */
@ -74,15 +75,17 @@ static struct clk mstp_clks[MSTP_NR] = {
[MSTP331] = MSTP(&sub_clk, SMSTPCR3, 31, 0), /* SCIFA6 */
[MSTP329] = MSTP(&r_clk, SMSTPCR3, 29, 0), /* CMT10 */
[MSTP323] = MSTP(&hp_clk, SMSTPCR3, 23, 0), /* I2C1 */
[MSTP403] = MSTP(&r_clk, SMSTPCR4, 0, 0), /* KEYSC0 */
[MSTP411] = MSTP(&hp_clk, SMSTPCR4, 11, 0), /* I2C3 */
[MSTP410] = MSTP(&hp_clk, SMSTPCR4, 10, 0), /* I2C4 */
[MSTP403] = MSTP(&r_clk, SMSTPCR4, 0, 0), /* KEYSC0 */
};
#define CLKDEV_DEV_ID(_id, _clk) { .dev_id = _id, .clk = _clk }
static struct clk_lookup lookups[] = {
/* MSTP32 clocks */
CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* I2C2 */
CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), /* I2C0 */
CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP219]), /* SCIFA7 */
CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]), /* SCIFA5 */
CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP206]), /* SCIFB */
@ -93,12 +96,10 @@ static struct clk_lookup lookups[] = {
CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]), /* SCIFA4 */
CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP331]), /* SCIFA6 */
CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]), /* CMT10 */
CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[MSTP403]), /* KEYSC0 */
CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), /* I2C0 */
CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* I2C1 */
CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* I2C2 */
CLKDEV_DEV_ID("i2c-sh_mobile.3", &mstp_clks[MSTP411]), /* I2C3 */
CLKDEV_DEV_ID("i2c-sh_mobile.4", &mstp_clks[MSTP410]), /* I2C4 */
CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[MSTP403]), /* KEYSC0 */
};
void __init sh73a0_clock_init(void)

2
arch/sh/include/mach-common/mach/romimage.h
View File

@ -4,7 +4,7 @@
#else /* __ASSEMBLY__ */
extern inline void mmcif_update_progress(int nr)
static inline void mmcif_update_progress(int nr)
{
}

2
arch/sh/include/mach-ecovec24/mach/romimage.h
View File

@ -35,7 +35,7 @@
#define HIZCRA 0xa4050158
#define PGDR 0xa405012c
extern inline void mmcif_update_progress(int nr)
static inline void mmcif_update_progress(int nr)
{
/* disable Hi-Z for LED pins */
__raw_writew(__raw_readw(HIZCRA) & ~(1 << 1), HIZCRA);

2
arch/sh/include/mach-kfr2r09/mach/romimage.h
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@ -23,7 +23,7 @@
#else /* __ASSEMBLY__ */
extern inline void mmcif_update_progress(int nr)
static inline void mmcif_update_progress(int nr)
{
}

26
include/linux/mmc/sh_mmcif.h
View File

@ -77,6 +77,9 @@ struct sh_mmcif_plat_data {
#define CLK_ENABLE (1 << 24) /* 1: output mmc clock */
#define CLK_CLEAR ((1 << 19) | (1 << 18) | (1 << 17) | (1 << 16))
#define CLK_SUP_PCLK ((1 << 19) | (1 << 18) | (1 << 17) | (1 << 16))
#define CLKDIV_4 (1<<16) /* mmc clock frequency.
* n: bus clock/(2^(n+1)) */
#define CLKDIV_256 (7<<16) /* mmc clock frequency. (see above) */
#define SRSPTO_256 ((1 << 13) | (0 << 12)) /* resp timeout */
#define SRBSYTO_29 ((1 << 11) | (1 << 10) | \
(1 << 9) | (1 << 8)) /* resp busy timeout */
@ -87,7 +90,7 @@ struct sh_mmcif_plat_data {
/* CE_VERSION */
#define SOFT_RST_ON (1 << 31)
#define SOFT_RST_OFF ~SOFT_RST_ON
#define SOFT_RST_OFF 0
static inline u32 sh_mmcif_readl(void __iomem *addr, int reg)
{
@ -175,12 +178,9 @@ static inline int sh_mmcif_boot_do_read(void __iomem *base,
static inline void sh_mmcif_boot_init(void __iomem *base)
{
unsigned long tmp;
/* reset */
tmp = sh_mmcif_readl(base, MMCIF_CE_VERSION);
sh_mmcif_writel(base, MMCIF_CE_VERSION, tmp | SOFT_RST_ON);
sh_mmcif_writel(base, MMCIF_CE_VERSION, tmp & SOFT_RST_OFF);
sh_mmcif_writel(base, MMCIF_CE_VERSION, SOFT_RST_ON);
sh_mmcif_writel(base, MMCIF_CE_VERSION, SOFT_RST_OFF);
/* byte swap */
sh_mmcif_writel(base, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP);
@ -188,14 +188,10 @@ static inline void sh_mmcif_boot_init(void __iomem *base)
/* Set block size in MMCIF hardware */
sh_mmcif_writel(base, MMCIF_CE_BLOCK_SET, SH_MMCIF_BBS);
/* Enable the clock, set it to Bus clock/256 (about 325Khz).
* It is unclear where 0x70000 comes from or if it is even needed.
* It is there for byte-compatibility with code that is known to
* work.
*/
/* Enable the clock, set it to Bus clock/256 (about 325Khz). */
sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL,
CLK_ENABLE | SRSPTO_256 | SRBSYTO_29 | SRWDTO_29 |
SCCSTO_29 | 0x70000);
CLK_ENABLE | CLKDIV_256 | SRSPTO_256 |
SRBSYTO_29 | SRWDTO_29 | SCCSTO_29);
/* CMD0 */
sh_mmcif_boot_cmd(base, 0x00000040, 0);
@ -220,7 +216,9 @@ static inline void sh_mmcif_boot_slurp(void __iomem *base,
unsigned long tmp;
/* In data transfer mode: Set clock to Bus clock/4 (about 20Mhz) */
sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL, 0x01012fff);
sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL,
CLK_ENABLE | CLKDIV_4 | SRSPTO_256 |
SRBSYTO_29 | SRWDTO_29 | SCCSTO_29);
/* CMD9 - Get CSD */
sh_mmcif_boot_cmd(base, 0x09806000, 0x00010000);