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drm/amd/powerplay: fix typo error when set clock gate state.

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Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Christian König<christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Rex Zhu 2016-07-20 18:13:47 +08:00 committed by Alex Deucher
parent b7e2e9f709
commit 0a6abefe9e
2 changed files with 2 additions and 2 deletions
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2
drivers/gpu/drm/amd/powerplay/hwmgr/fiji_clockpowergating.c
View File

@ -56,7 +56,7 @@ int fiji_phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
fiji_update_uvd_dpm(hwmgr, false);
cgs_set_clockgating_state(hwmgr->device,
AMD_IP_BLOCK_TYPE_UVD,
AMD_PG_STATE_UNGATE);
AMD_CG_STATE_UNGATE);
}
return 0;

2
drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_clockpowergating.c
View File

@ -116,7 +116,7 @@ int polaris10_phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
polaris10_update_uvd_dpm(hwmgr, false);
cgs_set_clockgating_state(hwmgr->device,
AMD_IP_BLOCK_TYPE_UVD,
AMD_PG_STATE_UNGATE);
AMD_CG_STATE_UNGATE);
}
return 0;