forked from Minki/linux
ARM: tegra: Correct polarity for Tegra114 PMIC interrupt
The ARM GIC only supports interrupts with either level-high or rising-edge types for SPIs. The interrupt type for the Palmas PMIC used for Tegra114 boards is specified as level-low which is invalid for the GIC. This has gone undetected because until recently, failures to set the interrupt type when the interrupts are mapped via firmware (such as device-tree) have not been reported. Since commits4b357daed6
("genirq: Look-up trigger type if not specified by caller") and1e2a7d7849
("irqdomain: Don't set type when mapping an IRQ"), failure to set the interrupt type will cause the requesting of the interrupt to fail and exposing incorrectly configured interrupts. Please note that although the interrupt type was never being set for the Palmas PMIC, it was still working fine, because the default type setting for the interrupt, 'level-high', happen to match the correct type for the interrupt. Finally, it should be noted that the Palmas interrupt from the PMIC is actually 'level-low', however, this interrupt signal is inverted by the Tegra PMC and so the GIC actually sees a 'level-high' interrupt which is what should be specified in the device-tree interrupt specifier. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Olof Johansson <olof@lixom.net>
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parent
633af91ddb
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0a10e85b6c
@ -897,7 +897,7 @@
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palmas: tps65913@58 {
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compatible = "ti,palmas";
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reg = <0x58>;
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interrupts = <0 86 IRQ_TYPE_LEVEL_LOW>;
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interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
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#interrupt-cells = <2>;
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interrupt-controller;
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@ -802,7 +802,7 @@
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palmas: pmic@58 {
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compatible = "ti,palmas";
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reg = <0x58>;
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interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
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interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
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#interrupt-cells = <2>;
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interrupt-controller;
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@ -63,7 +63,7 @@
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palmas: pmic@58 {
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compatible = "ti,palmas";
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reg = <0x58>;
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interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
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interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
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#interrupt-cells = <2>;
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interrupt-controller;
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