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powerpc/book3s64/radix: Rename CPU_FTR_P9_TLBIE_BUG feature flag

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Rename the #define to indicate this is related to store vs tlbie
ordering issue. In the next patch, we will be adding another feature
flag that is used to handles ERAT flush vs tlbie ordering issue.

Fixes: a5d4b5891c ("powerpc/mm: Fixup tlbie vs store ordering issue on POWER9")
Cc: stable@vger.kernel.org # v4.16+
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20190924035254.24612-2-aneesh.kumar@linux.ibm.com
This commit is contained in:
Aneesh Kumar K.V 2019-09-24 09:22:52 +05:30 committed by Michael Ellerman
parent 677733e296
commit 09ce98cacd
5 changed files with 9 additions and 9 deletions
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4
arch/powerpc/include/asm/cputable.h
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@ -209,7 +209,7 @@ static inline void cpu_feature_keys_init(void) { }
#define CPU_FTR_POWER9_DD2_1 LONG_ASM_CONST(0x0000080000000000) #define CPU_FTR_POWER9_DD2_1 LONG_ASM_CONST(0x0000080000000000)
#define CPU_FTR_P9_TM_HV_ASSIST LONG_ASM_CONST(0x0000100000000000) #define CPU_FTR_P9_TM_HV_ASSIST LONG_ASM_CONST(0x0000100000000000)
#define CPU_FTR_P9_TM_XER_SO_BUG LONG_ASM_CONST(0x0000200000000000) #define CPU_FTR_P9_TM_XER_SO_BUG LONG_ASM_CONST(0x0000200000000000)
#define CPU_FTR_P9_TLBIE_BUG LONG_ASM_CONST(0x0000400000000000) #define CPU_FTR_P9_TLBIE_STQ_BUG LONG_ASM_CONST(0x0000400000000000)
#define CPU_FTR_P9_TIDR LONG_ASM_CONST(0x0000800000000000) #define CPU_FTR_P9_TIDR LONG_ASM_CONST(0x0000800000000000)
#ifndef __ASSEMBLY__ #ifndef __ASSEMBLY__
@ -457,7 +457,7 @@ static inline void cpu_feature_keys_init(void) { }
CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \ CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_ARCH_207S | \ CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_ARCH_207S | \
CPU_FTR_TM_COMP | CPU_FTR_ARCH_300 | CPU_FTR_PKEY | \ CPU_FTR_TM_COMP | CPU_FTR_ARCH_300 | CPU_FTR_PKEY | \
CPU_FTR_P9_TLBIE_BUG | CPU_FTR_P9_TIDR) CPU_FTR_P9_TLBIE_STQ_BUG | CPU_FTR_P9_TIDR)
#define CPU_FTRS_POWER9_DD2_0 CPU_FTRS_POWER9 #define CPU_FTRS_POWER9_DD2_0 CPU_FTRS_POWER9
#define CPU_FTRS_POWER9_DD2_1 (CPU_FTRS_POWER9 | CPU_FTR_POWER9_DD2_1) #define CPU_FTRS_POWER9_DD2_1 (CPU_FTRS_POWER9 | CPU_FTR_POWER9_DD2_1)
#define CPU_FTRS_POWER9_DD2_2 (CPU_FTRS_POWER9 | CPU_FTR_POWER9_DD2_1 | \ #define CPU_FTRS_POWER9_DD2_2 (CPU_FTRS_POWER9 | CPU_FTR_POWER9_DD2_1 | \

6
arch/powerpc/kernel/dt_cpu_ftrs.c
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@ -706,14 +706,14 @@ static __init void update_tlbie_feature_flag(unsigned long pvr)
if ((pvr & 0xe000) == 0) { if ((pvr & 0xe000) == 0) {
/* Nimbus */ /* Nimbus */
if ((pvr & 0xfff) < 0x203) if ((pvr & 0xfff) < 0x203)
cur_cpu_spec->cpu_features |= CPU_FTR_P9_TLBIE_BUG; cur_cpu_spec->cpu_features |= CPU_FTR_P9_TLBIE_STQ_BUG;
} else if ((pvr & 0xc000) == 0) { } else if ((pvr & 0xc000) == 0) {
/* Cumulus */ /* Cumulus */
if ((pvr & 0xfff) < 0x103) if ((pvr & 0xfff) < 0x103)
cur_cpu_spec->cpu_features |= CPU_FTR_P9_TLBIE_BUG; cur_cpu_spec->cpu_features |= CPU_FTR_P9_TLBIE_STQ_BUG;
} else { } else {
WARN_ONCE(1, "Unknown PVR"); WARN_ONCE(1, "Unknown PVR");
cur_cpu_spec->cpu_features |= CPU_FTR_P9_TLBIE_BUG; cur_cpu_spec->cpu_features |= CPU_FTR_P9_TLBIE_STQ_BUG;
} }
} }
} }

2
arch/powerpc/kvm/book3s_hv_rm_mmu.c
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@ -451,7 +451,7 @@ static void do_tlbies(struct kvm *kvm, unsigned long *rbvalues,
"r" (rbvalues[i]), "r" (kvm->arch.lpid)); "r" (rbvalues[i]), "r" (kvm->arch.lpid));
} }
if (cpu_has_feature(CPU_FTR_P9_TLBIE_BUG)) { if (cpu_has_feature(CPU_FTR_P9_TLBIE_STQ_BUG)) {
/* /*
* Need the extra ptesync to make sure we don't * Need the extra ptesync to make sure we don't
* re-order the tlbie * re-order the tlbie

2
arch/powerpc/mm/book3s64/hash_native.c
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@ -199,7 +199,7 @@ static inline unsigned long ___tlbie(unsigned long vpn, int psize,
static inline void fixup_tlbie(unsigned long vpn, int psize, int apsize, int ssize) static inline void fixup_tlbie(unsigned long vpn, int psize, int apsize, int ssize)
{ {
if (cpu_has_feature(CPU_FTR_P9_TLBIE_BUG)) { if (cpu_has_feature(CPU_FTR_P9_TLBIE_STQ_BUG)) {
/* Need the extra ptesync to ensure we don't reorder tlbie*/ /* Need the extra ptesync to ensure we don't reorder tlbie*/
asm volatile("ptesync": : :"memory"); asm volatile("ptesync": : :"memory");
___tlbie(vpn, psize, apsize, ssize); ___tlbie(vpn, psize, apsize, ssize);

4
arch/powerpc/mm/book3s64/radix_tlb.c
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@ -201,7 +201,7 @@ static inline void fixup_tlbie(void)
unsigned long pid = 0; unsigned long pid = 0;
unsigned long va = ((1UL << 52) - 1); unsigned long va = ((1UL << 52) - 1);
if (cpu_has_feature(CPU_FTR_P9_TLBIE_BUG)) { if (cpu_has_feature(CPU_FTR_P9_TLBIE_STQ_BUG)) {
asm volatile("ptesync": : :"memory"); asm volatile("ptesync": : :"memory");
__tlbie_va(va, pid, mmu_get_ap(MMU_PAGE_64K), RIC_FLUSH_TLB); __tlbie_va(va, pid, mmu_get_ap(MMU_PAGE_64K), RIC_FLUSH_TLB);
} }
@ -211,7 +211,7 @@ static inline void fixup_tlbie_lpid(unsigned long lpid)
{ {
unsigned long va = ((1UL << 52) - 1); unsigned long va = ((1UL << 52) - 1);
if (cpu_has_feature(CPU_FTR_P9_TLBIE_BUG)) { if (cpu_has_feature(CPU_FTR_P9_TLBIE_STQ_BUG)) {
asm volatile("ptesync": : :"memory"); asm volatile("ptesync": : :"memory");
__tlbie_lpid_va(va, lpid, mmu_get_ap(MMU_PAGE_64K), RIC_FLUSH_TLB); __tlbie_lpid_va(va, lpid, mmu_get_ap(MMU_PAGE_64K), RIC_FLUSH_TLB);
} }