forked from Minki/linux
ARM: davinci: da850: add dsp clock definition
Added dsp clock definition, keyed to "davinci-rproc.0". DSP clocks is derived from pll0 sysclk1. Add a clock tree node for that too. Signed-off-by: Robert Tivy <rtivy@ti.com> [nsekhar@ti.com: merge addition of pll0 sysclk1 and dsp clock into one commit. Add PSC_FORCE to dsp clock node to handle the case where DSP does not go into IDLE and its clock needs to be disabled.] Signed-off-by: Sekhar Nori <nsekhar@ti.com>
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af47e6bb88
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09810a853b
@ -76,6 +76,13 @@ static struct clk pll0_aux_clk = {
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.flags = CLK_PLL | PRE_PLL,
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};
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static struct clk pll0_sysclk1 = {
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.name = "pll0_sysclk1",
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.parent = &pll0_clk,
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.flags = CLK_PLL,
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.div_reg = PLLDIV1,
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};
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static struct clk pll0_sysclk2 = {
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.name = "pll0_sysclk2",
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.parent = &pll0_clk,
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@ -368,10 +375,19 @@ static struct clk sata_clk = {
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.flags = PSC_FORCE,
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};
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static struct clk dsp_clk = {
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.name = "dsp",
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.parent = &pll0_sysclk1,
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.domain = DAVINCI_GPSC_DSPDOMAIN,
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.lpsc = DA8XX_LPSC0_GEM,
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.flags = PSC_LRST | PSC_FORCE,
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};
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static struct clk_lookup da850_clks[] = {
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CLK(NULL, "ref", &ref_clk),
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CLK(NULL, "pll0", &pll0_clk),
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CLK(NULL, "pll0_aux", &pll0_aux_clk),
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CLK(NULL, "pll0_sysclk1", &pll0_sysclk1),
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CLK(NULL, "pll0_sysclk2", &pll0_sysclk2),
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CLK(NULL, "pll0_sysclk3", &pll0_sysclk3),
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CLK(NULL, "pll0_sysclk4", &pll0_sysclk4),
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@ -413,6 +429,7 @@ static struct clk_lookup da850_clks[] = {
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CLK("spi_davinci.1", NULL, &spi1_clk),
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CLK("vpif", NULL, &vpif_clk),
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CLK("ahci", NULL, &sata_clk),
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CLK("davinci-rproc.0", NULL, &dsp_clk),
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CLK(NULL, NULL, NULL),
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};
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