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clocksource: armada-370-xp: Enable timer divider only when needed

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The current code sets the timer divider bits always. However, when
the 25 MHz timer is enabled, this is not needed and has no effect.
As this causes some confusion, rework the code so the divider is
set only when needed, i.e. when the 25 MHz timer is not in use.

Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
This commit is contained in:
Ezequiel Garcia
2013-12-02 11:39:56 +01:00
committed by Daniel Lezcano
parent fdca679d87
commit 08cb8e4609
1 changed files with 9 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files

18
drivers/clocksource/time-armada-370-xp.c
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@@ -76,6 +76,7 @@
static void __iomem *timer_base, *local_base; static void __iomem *timer_base, *local_base;
static unsigned int timer_clk; static unsigned int timer_clk;
static bool timer25Mhz = true; static bool timer25Mhz = true;
static u32 enable_mask;
/* /*
* Number of timer ticks per jiffy. * Number of timer ticks per jiffy.
@@ -121,8 +122,7 @@ armada_370_xp_clkevt_next_event(unsigned long delta,
/* /*
* Enable the timer. * Enable the timer.
*/ */
local_timer_ctrl_clrset(TIMER0_RELOAD_EN, local_timer_ctrl_clrset(TIMER0_RELOAD_EN, enable_mask);
TIMER0_EN | TIMER0_DIV(TIMER_DIVIDER_SHIFT));
return 0; return 0;
} }
@@ -141,9 +141,7 @@ armada_370_xp_clkevt_mode(enum clock_event_mode mode,
/* /*
* Enable timer. * Enable timer.
*/ */
local_timer_ctrl_clrset(0, TIMER0_RELOAD_EN | local_timer_ctrl_clrset(0, TIMER0_RELOAD_EN | enable_mask);
TIMER0_EN |
TIMER0_DIV(TIMER_DIVIDER_SHIFT));
} else { } else {
/* /*
* Disable timer. * Disable timer.
@@ -240,10 +238,13 @@ static void __init armada_370_xp_timer_common_init(struct device_node *np)
WARN_ON(!timer_base); WARN_ON(!timer_base);
local_base = of_iomap(np, 1); local_base = of_iomap(np, 1);
if (timer25Mhz) if (timer25Mhz) {
set = TIMER0_25MHZ; set = TIMER0_25MHZ;
else enable_mask = TIMER0_EN;
} else {
clr = TIMER0_25MHZ; clr = TIMER0_25MHZ;
enable_mask = TIMER0_EN | TIMER0_DIV(TIMER_DIVIDER_SHIFT);
}
timer_ctrl_clrset(clr, set); timer_ctrl_clrset(clr, set);
local_timer_ctrl_clrset(clr, set); local_timer_ctrl_clrset(clr, set);
@@ -267,8 +268,7 @@ static void __init armada_370_xp_timer_common_init(struct device_node *np)
writel(0xffffffff, timer_base + TIMER0_VAL_OFF); writel(0xffffffff, timer_base + TIMER0_VAL_OFF);
writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF); writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF);
timer_ctrl_clrset(0, TIMER0_EN | TIMER0_RELOAD_EN | timer_ctrl_clrset(0, TIMER0_RELOAD_EN | enable_mask);
TIMER0_DIV(TIMER_DIVIDER_SHIFT));
clocksource_mmio_init(timer_base + TIMER0_VAL_OFF, clocksource_mmio_init(timer_base + TIMER0_VAL_OFF,
"armada_370_xp_clocksource", "armada_370_xp_clocksource",