forked from Minki/linux
This pull request contains Broadcom ARM-based machine/platform files
changes for 4.18, please pull the following: - Doug updates arch/arm/include/asm/cpuinfo.h such that this header file can be used by both C and assembly code. This particular change will also be included in a Sunxi pull request to support A83T SMP support. - Doug also updates our DEBUG_LL routine to support newer chips such as 7278 which have a version 7 memory map which moves the registers from physical address 0xf000_0000 down to 0x0800_0000. This requires us to look up the processor MIDR and determine the base address from the PERIPHBASE register. - Florian updates the Brahma-B15 read-ahead cache implementation such that it works on the Brahma-B53 CPUs, which also have an identical read-ahead cache implementation, with a different set of offsets. He also provides the Brahma-B15 MIDR definition such that it can be used by other pieces of code in the future. -----BEGIN PGP SIGNATURE----- iQIcBAABCAAGBQJa9c1BAAoJEIfQlpxEBwcEydEP/0QRDdSmZxpfLKBekgkUZ30t p7EwYjexdAscxuCJVKW13Tmdzx30XBJA33m+r45FzUzUpYsc/tKZoUC1NBMsyNnw q3cFE26ghhdoKCFTKVnr03Alo6PaJWFQM1uxx5bIIh/lyFePX64oD77Qtu7HOpgL w+OmOokkEymqjDyaThu4G3UsgiI2q+PaIlXo1uCOZqfsF2KtgmEmV4iLyOyPrpbn G7mDAFZ2NkNTBfjpgFkqS5qiG3AijKFTaWB2CwBvkq8o7rx4qO/4cHgRQhdoJ079 Q0hxnMhYIw5ixgCntFZz83XRX4XKRIAwXFrSaMb1iWCdbxMWnFyhV/QBV6NzVUNp EynUDG2u4ieCajfzeu0Cj6DCLauZqtqxxuthBvOIoYBUllFv3I/PhEJijkk1iYCy QWe/wtg/0ED4oPltm92oDtUU3TjKyJquWBKjO1loOAnstxG+ZJcIzLiIn6AsyrSj o2tuPHP6xgQRmAei3M7QrSipsliOfKi3XWuu2+mMUKXW3WyHTc5AqLtmJWKxJJCO 6Ts2gBFp9Ue/8u4WV0fUZ/MS5xyWZjhZQ6bVi7bpu2WFtN7p4YfyER/J0jDeB5lk Jjr+oPIVALYf8moSpm1l2Omx8gpwM/nd2a0dUyJ03mPDd697kRc/B0AqtSdR2S0H skn8/rJYpVr5oI4im7Zi =21hD -----END PGP SIGNATURE----- Merge tag 'arm-soc/for-4.18/soc' of https://github.com/Broadcom/stblinux into next/soc This pull request contains Broadcom ARM-based machine/platform files changes for 4.18, please pull the following: - Doug updates arch/arm/include/asm/cpuinfo.h such that this header file can be used by both C and assembly code. This particular change will also be included in a Sunxi pull request to support A83T SMP support. - Doug also updates our DEBUG_LL routine to support newer chips such as 7278 which have a version 7 memory map which moves the registers from physical address 0xf000_0000 down to 0x0800_0000. This requires us to look up the processor MIDR and determine the base address from the PERIPHBASE register. - Florian updates the Brahma-B15 read-ahead cache implementation such that it works on the Brahma-B53 CPUs, which also have an identical read-ahead cache implementation, with a different set of offsets. He also provides the Brahma-B15 MIDR definition such that it can be used by other pieces of code in the future. * tag 'arm-soc/for-4.18/soc' of https://github.com/Broadcom/stblinux: ARM: brcmstb: Add support for the V7 memory map ARM: add Broadcom Brahma-B15 main ID definition ARM: add Broadcom Brahma-B53 main ID definition ARM: Allow this header to be included by assembly files ARM: B15: Update to support Brahma-B53 Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
08a5f1ac35
@ -2,9 +2,6 @@
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#ifndef __ASM_ARM_CPUTYPE_H
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#define __ASM_ARM_CPUTYPE_H
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#include <linux/stringify.h>
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#include <linux/kernel.h>
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#define CPUID_ID 0
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#define CPUID_CACHETYPE 1
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#define CPUID_TCM 2
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@ -62,6 +59,7 @@
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((mpidr >> (MPIDR_LEVEL_BITS * level)) & MPIDR_LEVEL_MASK)
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#define ARM_CPU_IMP_ARM 0x41
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#define ARM_CPU_IMP_BRCM 0x42
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#define ARM_CPU_IMP_DEC 0x44
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#define ARM_CPU_IMP_INTEL 0x69
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@ -79,6 +77,10 @@
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#define ARM_CPU_PART_CORTEX_A15 0x4100c0f0
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#define ARM_CPU_PART_MASK 0xff00fff0
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/* Broadcom implemented processors */
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#define ARM_CPU_PART_BRAHMA_B15 0x420000f0
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#define ARM_CPU_PART_BRAHMA_B53 0x42001000
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/* DEC implemented cores */
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#define ARM_CPU_PART_SA1100 0x4400a110
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@ -98,6 +100,11 @@
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/* Qualcomm implemented cores */
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#define ARM_CPU_PART_SCORPION 0x510002d0
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#ifndef __ASSEMBLY__
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#include <linux/stringify.h>
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#include <linux/kernel.h>
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extern unsigned int processor_id;
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#ifdef CONFIG_CPU_CP15
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@ -326,4 +333,6 @@ static inline int __attribute_const__ cpuid_feature_extract_field(u32 features,
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#define cpuid_feature_extract(reg, field) \
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cpuid_feature_extract_field(read_cpuid_ext(reg), field)
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#endif /* __ASSEMBLY__ */
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#endif
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@ -11,20 +11,25 @@
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* GNU General Public License for more details.
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*/
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#include <linux/serial_reg.h>
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#include <asm/cputype.h>
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/* Physical register offset and virtual register offset */
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#define REG_PHYS_BASE 0xf0000000
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#define REG_PHYS_BASE_V7 0x08000000
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#define REG_VIRT_BASE 0xfc000000
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#define REG_PHYS_ADDR(x) ((x) + REG_PHYS_BASE)
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#define REG_PHYS_ADDR_V7(x) ((x) + REG_PHYS_BASE_V7)
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/* Product id can be read from here */
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#define SUN_TOP_CTRL_BASE REG_PHYS_ADDR(0x404000)
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#define SUN_TOP_CTRL_BASE_V7 REG_PHYS_ADDR_V7(0x404000)
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#define UARTA_3390 REG_PHYS_ADDR(0x40a900)
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#define UARTA_7250 REG_PHYS_ADDR(0x40b400)
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#define UARTA_7260 REG_PHYS_ADDR(0x40c000)
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#define UARTA_7268 UARTA_7260
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#define UARTA_7271 UARTA_7268
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#define UARTA_7278 REG_PHYS_ADDR_V7(0x40c000)
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#define UARTA_7364 REG_PHYS_ADDR(0x40b000)
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#define UARTA_7366 UARTA_7364
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#define UARTA_74371 REG_PHYS_ADDR(0x406b00)
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@ -55,8 +60,21 @@
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mov \rv, #0 @ yes; record init is done
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str \rv, [\tmp]
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/* Check for V7 memory map if B53 */
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mrc p15, 0, \rv, c0, c0, 0 @ get Main ID register
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ldr \rp, =ARM_CPU_PART_MASK
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and \rv, \rv, \rp
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ldr \rp, =ARM_CPU_PART_BRAHMA_B53 @ check for B53 CPU
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cmp \rv, \rp
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bne 10f
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/* if PERIPHBASE doesn't overlap REG_PHYS_BASE use V7 map */
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mrc p15, 1, \rv, c15, c3, 0 @ get PERIPHBASE from CBAR
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ands \rv, \rv, #REG_PHYS_BASE
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ldreq \rp, =SUN_TOP_CTRL_BASE_V7
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/* Check SUN_TOP_CTRL base */
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ldr \rp, =SUN_TOP_CTRL_BASE @ load SUN_TOP_CTRL PA
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10: ldrne \rp, =SUN_TOP_CTRL_BASE @ load SUN_TOP_CTRL PA
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ldr \rv, [\rp, #0] @ get register contents
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ARM_BE8( rev \rv, \rv )
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and \rv, \rv, #0xffffff00 @ strip revision bits [7:0]
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@ -72,6 +90,7 @@ ARM_BE8( rev \rv, \rv )
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27: checkuart(\rp, \rv, 0x07437100, 74371)
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28: checkuart(\rp, \rv, 0x74390000, 7439)
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29: checkuart(\rp, \rv, 0x74450000, 7445)
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30: checkuart(\rp, \rv, 0x72780000, 7278)
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/* No valid UART found */
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90: mov \rp, #0
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@ -33,7 +33,10 @@ extern void v7_flush_kern_cache_all(void);
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#define RAC_CPU_SHIFT (8)
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#define RACCFG_MASK (0xff)
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#define RAC_CONFIG1_REG (0x7c)
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#define RAC_FLUSH_REG (0x80)
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/* Brahma-B15 is a quad-core only design */
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#define B15_RAC_FLUSH_REG (0x80)
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/* Brahma-B53 is an octo-core design */
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#define B53_RAC_FLUSH_REG (0x84)
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#define FLUSH_RAC (1 << 0)
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/* Bitmask to enable instruction and data prefetching with a 256-bytes stride */
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@ -52,6 +55,7 @@ static void __iomem *b15_rac_base;
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static DEFINE_SPINLOCK(rac_lock);
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static u32 rac_config0_reg;
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static u32 rac_flush_offset;
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/* Initialization flag to avoid checking for b15_rac_base, and to prevent
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* multi-platform kernels from crashing here as well.
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@ -70,14 +74,14 @@ static inline void __b15_rac_flush(void)
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{
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u32 reg;
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__raw_writel(FLUSH_RAC, b15_rac_base + RAC_FLUSH_REG);
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__raw_writel(FLUSH_RAC, b15_rac_base + rac_flush_offset);
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do {
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/* This dmb() is required to force the Bus Interface Unit
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* to clean oustanding writes, and forces an idle cycle
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* to be inserted.
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*/
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dmb();
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reg = __raw_readl(b15_rac_base + RAC_FLUSH_REG);
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reg = __raw_readl(b15_rac_base + rac_flush_offset);
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} while (reg & FLUSH_RAC);
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}
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@ -287,7 +291,7 @@ static struct syscore_ops b15_rac_syscore_ops = {
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static int __init b15_rac_init(void)
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{
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struct device_node *dn;
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struct device_node *dn, *cpu_dn;
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int ret = 0, cpu;
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u32 reg, en_mask = 0;
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@ -305,6 +309,24 @@ static int __init b15_rac_init(void)
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goto out;
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}
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cpu_dn = of_get_cpu_node(0, NULL);
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if (!cpu_dn) {
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ret = -ENODEV;
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goto out;
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}
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if (of_device_is_compatible(cpu_dn, "brcm,brahma-b15"))
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rac_flush_offset = B15_RAC_FLUSH_REG;
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else if (of_device_is_compatible(cpu_dn, "brcm,brahma-b53"))
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rac_flush_offset = B53_RAC_FLUSH_REG;
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else {
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pr_err("Unsupported CPU\n");
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of_node_put(cpu_dn);
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ret = -EINVAL;
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goto out;
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}
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of_node_put(cpu_dn);
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ret = register_reboot_notifier(&b15_rac_reboot_nb);
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if (ret) {
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pr_err("failed to register reboot notifier\n");
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