forked from Minki/linux
scsi: ufs: Do not clear the DL layer timers
During power mode change, PACP_PWR_Req frame sends PAPowerModeUserData parameters (and they are considered valid by device if Flags[4] - UserDataValid bit is set in the same frame). Currently we don't set these PAPowerModeUserData parameters and hardware always sets UserDataValid bit which would clear all the DL layer timeout values of the peer device after the power mode change. This change sets the PAPowerModeUserData[0..5] to UniPro specification recommended default values, in addition we are also setting the relevant DME_LOCAL_* timer attributes as required by UFS HCI specification. Link: https://lore.kernel.org/r/0101016ed3d688a4-cfaeb1c9-238b-46c4-9c89-d48c410ba325-000000@us-west-2.amazonses.com Reviewed-by: Avri Altman <avri.altman@wdc.com> Reviewed-by: Bean Huo <beanhuo@micron.com> Signed-off-by: Can Guo <cang@codeaurora.org> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
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@ -4033,6 +4033,26 @@ static int ufshcd_change_power_mode(struct ufs_hba *hba,
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ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES),
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ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES),
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pwr_mode->hs_rate);
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pwr_mode->hs_rate);
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ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0),
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DL_FC0ProtectionTimeOutVal_Default);
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ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1),
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DL_TC0ReplayTimeOutVal_Default);
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ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2),
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DL_AFC0ReqTimeOutVal_Default);
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ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA3),
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DL_FC1ProtectionTimeOutVal_Default);
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ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA4),
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DL_TC1ReplayTimeOutVal_Default);
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ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA5),
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DL_AFC1ReqTimeOutVal_Default);
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ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalFC0ProtectionTimeOutVal),
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DL_FC0ProtectionTimeOutVal_Default);
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ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalTC0ReplayTimeOutVal),
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DL_TC0ReplayTimeOutVal_Default);
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ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalAFC0ReqTimeOutVal),
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DL_AFC0ReqTimeOutVal_Default);
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ret = ufshcd_uic_change_pwr_mode(hba, pwr_mode->pwr_rx << 4
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ret = ufshcd_uic_change_pwr_mode(hba, pwr_mode->pwr_rx << 4
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| pwr_mode->pwr_tx);
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| pwr_mode->pwr_tx);
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@ -161,6 +161,17 @@
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/* PHY Adapter Protocol Constants */
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/* PHY Adapter Protocol Constants */
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#define PA_MAXDATALANES 4
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#define PA_MAXDATALANES 4
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#define DL_FC0ProtectionTimeOutVal_Default 8191
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#define DL_TC0ReplayTimeOutVal_Default 65535
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#define DL_AFC0ReqTimeOutVal_Default 32767
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#define DL_FC1ProtectionTimeOutVal_Default 8191
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#define DL_TC1ReplayTimeOutVal_Default 65535
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#define DL_AFC1ReqTimeOutVal_Default 32767
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#define DME_LocalFC0ProtectionTimeOutVal 0xD041
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#define DME_LocalTC0ReplayTimeOutVal 0xD042
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#define DME_LocalAFC0ReqTimeOutVal 0xD043
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/* PA power modes */
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/* PA power modes */
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enum {
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enum {
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FAST_MODE = 1,
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FAST_MODE = 1,
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