forked from Minki/linux
staging: rtl8192su: r8192S_phy.c, remove unused code; 2nd part
Signed-off-by: Florian Schilhabel <florian.c.schilhabel@googlemail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
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dc7bbaa4ff
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0825c40f95
@ -27,16 +27,12 @@
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#include "ieee80211/dot11d.h"
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/*---------------------------Define Local Constant---------------------------*/
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/* Channel switch:The size of command tables for switch channel*/
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#define MAX_PRECMD_CNT 16
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#define MAX_RFDEPENDCMD_CNT 16
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#define MAX_POSTCMD_CNT 16
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#define MAX_DOZE_WAITING_TIMES_9x 64
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/*------------------------Define local variable------------------------------*/
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// 2004-05-11
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static u32
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phy_CalculateBitShift(u32 BitMask);
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static RT_STATUS
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@ -79,8 +75,6 @@ void phy_SetFwCmdIOCallback(struct net_device* dev);
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// - Only use on RTL8192S USB interface.
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// - PASSIVE LEVEL
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//
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// Created by Roger, 2008.09.06.
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//
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//use in phy only
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u32 phy_QueryUsbBBReg(struct net_device* dev, u32 RegAddr)
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{
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@ -144,9 +138,6 @@ u32 phy_QueryUsbBBReg(struct net_device* dev, u32 RegAddr)
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// Assumption:
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// - Only use on RTL8192S USB interface.
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// - PASSIVE LEVEL
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//
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// Created by Roger, 2008.09.06.
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//
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//use in phy only
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void
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phy_SetUsbBBReg(struct net_device* dev,u32 RegAddr,u32 Data)
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@ -175,7 +166,6 @@ phy_SetUsbBBReg(struct net_device* dev,u32 RegAddr,u32 Data)
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}
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priv->bChangeBBInProgress = true;
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//printk("**************%s: RegAddr:%x Data:%x\n", __FUNCTION__,RegAddr, Data);
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write_nic_dword(dev, RegAddr, Data);
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priv->bChangeBBInProgress = false;
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@ -199,9 +189,7 @@ u32 phy_QueryUsbRFReg( struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Of
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{
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struct r8192_priv *priv = ieee80211_priv(dev);
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//u32 value = 0, ReturnValue = 0;
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u32 ReturnValue = 0;
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//u32 tmplong,tmplong2;
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u8 PollingCnt = 50;
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u8 RFWaitCounter = 0;
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@ -213,8 +201,6 @@ u32 phy_QueryUsbRFReg( struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Of
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//
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while(priv->bChangeRFInProgress)
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{
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//PlatformReleaseSpinLock(Adapter, RT_RF_OPERATE_SPINLOCK);
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//spin_lock_irqsave(&priv->rf_lock, flags); //LZM,090318
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down(&priv->rf_sem);
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RFWaitCounter ++;
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@ -228,14 +214,10 @@ u32 phy_QueryUsbRFReg( struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Of
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}
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else
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{
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//PlatformAcquireSpinLock(Adapter, RT_RF_OPERATE_SPINLOCK);
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}
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}
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priv->bChangeRFInProgress = true;
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//PlatformReleaseSpinLock(Adapter, RT_RF_OPERATE_SPINLOCK);
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Offset &= 0x3f; //RF_Offset= 0x00~0x3F
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write_nic_dword(dev, RF_BB_CMD_ADDR, 0xF0000002|
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@ -294,7 +276,7 @@ void phy_SetUsbRFReg(struct net_device* dev,RF90_RADIO_PATH_E eRFPath,u32 RegAdd
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RT_TRACE(COMP_RF, "phy_SetUsbRFReg(): Wait 1 ms (%d times)...\n", RFWaitCounter);
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msleep(1); // 1 ms
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if((RFWaitCounter > 100))// || RT_USB_CANNOT_IO(Adapter))
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if((RFWaitCounter > 100))
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{
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RT_TRACE(COMP_RF, "phy_SetUsbRFReg(): (%d) Wait too logn to query BB!!\n", RFWaitCounter);
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return;
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@ -330,11 +312,6 @@ void phy_SetUsbRFReg(struct net_device* dev,RF90_RADIO_PATH_E eRFPath,u32 RegAdd
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}
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/*---------------------Define local function prototype-----------------------*/
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/*----------------------------Function Body----------------------------------*/
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//
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// 1. BB register R/W API
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//
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@ -352,8 +329,6 @@ void phy_SetUsbRFReg(struct net_device* dev,RF90_RADIO_PATH_E eRFPath,u32 RegAdd
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* Return: u32 Data //The readback register value
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* Note: This function is equal to "GetRegSetting" in PHY programming guide
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*/
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//use phy dm core 8225 8256 6052
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//u32 PHY_QueryBBReg(struct net_device* dev,u32 RegAddr, u32 BitMask)
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u32 rtl8192_QueryBBReg(struct net_device* dev, u32 RegAddr, u32 BitMask)
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{
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@ -368,7 +343,6 @@ u32 rtl8192_QueryBBReg(struct net_device* dev, u32 RegAddr, u32 BitMask)
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// infinite cycle.
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// 2008.09.06.
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//
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//#if ((HAL_CODE_BASE == RTL8192_S) && (DEV_BUS_TYPE==USB_INTERFACE))
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if(IS_BB_REG_OFFSET_92S(RegAddr))
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{
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@ -410,8 +384,6 @@ u32 rtl8192_QueryBBReg(struct net_device* dev, u32 RegAddr, u32 BitMask)
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* Return: None
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* Note: This function is equal to "PutRegSetting" in PHY programming guide
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*/
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//use phy dm core 8225 8256
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//void PHY_SetBBReg(struct net_device* dev,u32 RegAddr, u32 BitMask, u32 Data )
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void rtl8192_setBBreg(struct net_device* dev, u32 RegAddr, u32 BitMask, u32 Data)
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{
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u32 OriginalValue, BitShift, NewValue;
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@ -425,7 +397,6 @@ void rtl8192_setBBreg(struct net_device* dev, u32 RegAddr, u32 BitMask, u32 Data
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// infinite cycle.
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// 2008.09.06.
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//
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//#if ((HAL_CODE_BASE == RTL8192_S) && (DEV_BUS_TYPE==USB_INTERFACE))
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if(IS_BB_REG_OFFSET_92S(RegAddr))
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{
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if((RegAddr & 0x03) != 0)
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@ -479,8 +450,6 @@ void rtl8192_setBBreg(struct net_device* dev, u32 RegAddr, u32 BitMask, u32 Data
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* Return: u32 Readback value
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* Note: This function is equal to "GetRFRegSetting" in PHY programming guide
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*/
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//in dm 8256 and phy
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//u32 PHY_QueryRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask)
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u32 rtl8192_phy_QueryRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask)
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{
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u32 Original_Value, Readback_Value, BitShift;//, flags;
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@ -560,8 +529,6 @@ void rtl8192_phy_SetRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32
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// <Roger_Notes> Due to 8051 operation cycle (limitation cycle: 6us) and 1-Byte access issue, we should use
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// 4181 to access Base Band instead of 8051 on USB interface to make sure that access could be done in
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// infinite cycle.
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// 2008.09.06.
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//
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if (BitMask != bRFRegOffsetMask) // RF data is 12 bits only
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{
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@ -905,26 +872,6 @@ phy_ConfigBBWithHeaderFile(struct net_device* dev,u8 ConfigType)
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u32* Rtl819XAGCTAB_Array_Table;
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u16 PHY_REGArrayLen, AGCTAB_ArrayLen;
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/*if(Adapter->bInHctTest)
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{
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AGCTAB_ArrayLen = AGCTAB_ArrayLengthDTM;
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Rtl819XAGCTAB_Array_Table = Rtl819XAGCTAB_ArrayDTM;
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if(pHalData->RF_Type == RF_2T4R)
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{
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PHY_REGArrayLen = PHY_REGArrayLengthDTM;
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Rtl819XPHY_REGArray_Table = Rtl819XPHY_REGArrayDTM;
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}
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else if (pHalData->RF_Type == RF_1T2R)
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{
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PHY_REGArrayLen = PHY_REG_1T2RArrayLengthDTM;
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Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_1T2RArrayDTM;
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}
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}
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else
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*/
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AGCTAB_ArrayLen = AGCTAB_ArrayLength;
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Rtl819XAGCTAB_Array_Table = Rtl819XAGCTAB_Array;
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PHY_REGArrayLen = PHY_REG_2T2RArrayLength; // Default RF_type: 2T2R
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@ -1026,8 +973,6 @@ phy_ConfigBBWithPgHeaderFile(struct net_device* dev,u8 ConfigType)
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*
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* Note: Delay may be required for RF configuration
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*---------------------------------------------------------------------------*/
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//in 8256 phy_RF8256_Config_ParaFile only
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//RT_STATUS PHY_ConfigRFWithHeaderFile(struct net_device* dev,RF90_RADIO_PATH_E eRFPath)
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u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device* dev, RF90_RADIO_PATH_E eRFPath)
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{
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@ -1536,9 +1481,6 @@ static bool phy_SetRFPowerState8192SU(struct net_device* dev,RT_RF_POWER_STATE e
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break;
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//
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//RF Off/Sleep sequence. Designed/tested from SD4 Scott, SD1 Grent and Jonbon.
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// Added by Bruce, 2008-11-22.
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//
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//==================================================================
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// (0) Disable FW BB reset checking
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write_nic_dword(dev, WFM5, FW_BB_RESET_DISABLE);
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@ -1746,14 +1688,6 @@ PHY_GetTxPowerLevel8192S(
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// RF B HT OFDM pwr-RFA HT OFDM pwr
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ant_pwr_diff = priv->RfTxPwrLevelOfdm2T[1][index] -
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priv->RfTxPwrLevelOfdm2T[0][index];
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// RF B (HT OFDM pwr+legacy-ht-diff) -(RFA HT OFDM pwr+legacy-ht-diff)
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// We can not handle Path B&A HT/Legacy pwr diff for 92S now.
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//RTPRINT(FPHY, PHY_TXPWR, ("CH-%d HT40 A/B Pwr index = %x/%x(%d/%d)\n",
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//channel, priv->RfTxPwrLevelOfdm2T[0][index],
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//priv->RfTxPwrLevelOfdm2T[1][index],
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//priv->RfTxPwrLevelOfdm2T[0][index],
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//priv->RfTxPwrLevelOfdm2T[1][index]));
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ht20pwr[0] = ht40pwr[0] = priv->RfTxPwrLevelOfdm2T[0][index];
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ht20pwr[1] = ht40pwr[1] = priv->RfTxPwrLevelOfdm2T[1][index];
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@ -1786,10 +1720,6 @@ PHY_GetTxPowerLevel8192S(
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// RF B HT OFDM pwr-RFA HT OFDM pwr
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if (priv->rf_type == RF_2T2R)
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ant_pwr_diff = ht20pwr[1] - ht20pwr[0];
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//RTPRINT(FPHY, PHY_TXPWR,
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//("HT20 to HT40 pwrdiff[A/B]=%d/%d, ant_pwr_diff=%d(B-A=%d-%d)\n",
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//pwrdiff[0], pwrdiff[1], ant_pwr_diff, ht20pwr[1], ht20pwr[0]));
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}
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// Band Edge scheme is enabled for FCC mode
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@ -1834,18 +1764,12 @@ PHY_GetTxPowerLevel8192S(
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{
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if (channel <= 1 || channel >= 11)
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{
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//RTPRINT(FPHY, PHY_TXPWR,
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//("HT20 Band-edge pwrdiff[A/B]=%d/%d, ant_pwr_diff=%d(B-A=%d-%d)\n",
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//pwrdiff[0], pwrdiff[1], ant_pwr_diff, ht20pwr[1], ht20pwr[0]));
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}
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}
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else
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{
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if (channel <= 3 || channel >= 9)
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{
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//RTPRINT(FPHY, PHY_TXPWR,
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//("HT40 Band-edge pwrdiff[A/B]=%d/%d, ant_pwr_diff=%d(B-A=%d-%d)\n",
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//pwrdiff[0], pwrdiff[1], ant_pwr_diff, ht40pwr[1], ht40pwr[0]));
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}
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}
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}
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@ -1858,10 +1782,6 @@ PHY_GetTxPowerLevel8192S(
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if(ant_pwr_diff < -8)
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ant_pwr_diff = -8;
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//RTPRINT(FPHY, PHY_TXPWR,
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//("CCK/HT Power index = %x/%x(%d/%d), ant_pwr_diff=%d\n",
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//powerlevel, powerlevelOFDM24G, powerlevel, powerlevelOFDM24G, ant_pwr_diff));
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ant_pwr_diff &= 0xf;
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// Antenna TX power difference
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@ -1887,7 +1807,6 @@ PHY_GetTxPowerLevel8192S(
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// TODO:
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// 1. 802.11h power contraint
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//
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// 071011, by rcnjko.
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//
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#ifdef TODO //WB, 11h has not implemented now.
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if( priv->ieee80211->iw_mode != IW_MODE_INFRA && priv->bWithCcxCellPwr &&
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@ -1956,8 +1875,6 @@ PHY_GetTxPowerLevel8192S(
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//
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// TODO:
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// A mode.
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// By Bruce, 2008-02-04.
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// no use temp
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bool PHY_UpdateTxPowerDbm8192S(struct net_device* dev, long powerInDbm)
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{
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struct r8192_priv *priv = ieee80211_priv(dev);
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@ -1999,8 +1916,6 @@ bool PHY_UpdateTxPowerDbm8192S(struct net_device* dev, long powerInDbm)
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Description:
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When beacon interval is changed, the values of the
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hw registers should be modified.
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By tynli, 2008.10.24.
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*/
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extern void PHY_SetBeaconHwReg( struct net_device* dev, u16 BeaconInterval)
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@ -2017,7 +1932,6 @@ extern void PHY_SetBeaconHwReg( struct net_device* dev, u16 BeaconInterval)
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// Map dBm into Tx power index according to
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// current HW model, for example, RF and PA, and
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// current wireless mode.
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// By Bruce, 2008-01-29.
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// use in phy only
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static u8 phy_DbmToTxPwrIdx(
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struct net_device* dev,
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@ -2034,7 +1948,6 @@ static u8 phy_DbmToTxPwrIdx(
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// 3dbm, and OFDM HT equals to 0dbm repectively.
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// Note:
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// The mapping may be different by different NICs. Do not use this formula for what needs accurate result.
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// By Bruce, 2008-01-29.
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//
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switch(WirelessMode)
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{
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@ -2070,7 +1983,6 @@ static u8 phy_DbmToTxPwrIdx(
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// Map Tx power index into dBm according to
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// current HW model, for example, RF and PA, and
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// current wireless mode.
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// By Bruce, 2008-01-29.
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// use in phy only
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static long phy_TxPwrIdxToDbm(
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struct net_device* dev,
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@ -2087,7 +1999,6 @@ static long phy_TxPwrIdxToDbm(
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// 3dbm, and OFDM HT equals to 0dbm repectively.
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// Note:
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// The mapping may be different by different NICs. Do not use this formula for what needs accurate result.
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// By Bruce, 2008-01-29.
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//
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switch(WirelessMode)
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{
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@ -2253,7 +2164,6 @@ void PHY_SetBWModeCallback8192S(struct net_device *dev)
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rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1));
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rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC);
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//rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00300000, 3);
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if (priv->card_8192_version >= VERSION_8192S_BCUT)
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write_nic_byte(dev, rFPGA0_AnalogParameter2, 0x18);
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@ -2336,7 +2246,7 @@ void rtl8192_SetBWMode(struct net_device *dev, HT_CHANNEL_WIDTH Bandwidth, HT_EX
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else
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priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
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if((priv->up) )// && !(RT_CANNOT_IO(Adapter) && Adapter->bInSetPower) )
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if((priv->up) )
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{
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SetBWModeCallback8192SUsbWorkItem(dev);
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}
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@ -2473,8 +2383,7 @@ u8 rtl8192_phy_SwChnl(struct net_device* dev, u8 channel)
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// The following procedure is operted according to SwChanlCallback8190Pci().
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// However, this procedure is performed synchronously which should be running under
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// passive level.
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//
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//not understand it
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void PHY_SwChnlPhy8192S( // Only called during initialize
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struct net_device* dev,
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u8 channel
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@ -2917,21 +2826,6 @@ extern void PHY_IQCalibrateBcut(struct net_device* dev)
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//
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// 1. Save e70~ee0 register setting, and load calibration setting
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//
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/*
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0xee0[31:0]=0x3fed92fb;
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0xedc[31:0] =0x3fed92fb;
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0xe70[31:0] =0x3fed92fb;
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0xe74[31:0] =0x3fed92fb;
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0xe78[31:0] =0x3fed92fb;
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0xe7c[31:0]= 0x3fed92fb;
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0xe80[31:0]= 0x3fed92fb;
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0xe84[31:0]= 0x3fed92fb;
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0xe88[31:0]= 0x3fed92fb;
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0xe8c[31:0]= 0x3fed92fb;
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0xed0[31:0]= 0x3fed92fb;
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0xed4[31:0]= 0x3fed92fb;
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0xed8[31:0]= 0x3fed92fb;
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*/
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calibrate_set [0] = 0xee0;
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calibrate_set [1] = 0xedc;
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calibrate_set [2] = 0xe70;
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@ -3017,7 +2911,6 @@ extern void PHY_IQCalibrateBcut(struct net_device* dev)
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if (!RfPiEnable) //if original is SI mode, then switch to PI mode.
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{
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//DbgPrint("IQK Switch back to SI mode\n");
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rtl8192_setBBreg(dev, 0x820, bMaskDWord, 0x01000000);
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rtl8192_setBBreg(dev, 0x828, bMaskDWord, 0x01000000);
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}
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