drm/i915: use id from intel_shared_dpll.info
Replace all users of pll->id to use pll->info->id. In functions using this more than once it was preferred to add an id variable to make the code easier to read. Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180320220637.21480-6-lucas.demarchi@intel.com
This commit is contained in:
Lucas De Marchi
Rodrigo Vivi
parent
72f775fa28
commit
0823eb9c52
@ -3286,7 +3286,7 @@ static int i915_shared_dplls_info(struct seq_file *m, void *unused)
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struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
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seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->info->name,
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pll->id);
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pll->info->id);
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seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n",
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pll->state.crtc_mask, pll->active_mask, yesno(pll->on));
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seq_printf(m, " tracked hardware state:\n");
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@ -994,7 +994,7 @@ static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
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static uint32_t hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
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{
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switch (pll->id) {
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switch (pll->info->id) {
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case DPLL_ID_WRPLL1:
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return PORT_CLK_SEL_WRPLL1;
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case DPLL_ID_WRPLL2:
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@ -1008,7 +1008,7 @@ static uint32_t hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
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case DPLL_ID_LCPLL_2700:
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return PORT_CLK_SEL_LCPLL_2700;
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default:
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MISSING_CASE(pll->id);
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MISSING_CASE(pll->info->id);
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return PORT_CLK_SEL_NONE;
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}
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}
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@ -2250,7 +2250,7 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder,
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/* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
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val = I915_READ(DPCLKA_CFGCR0);
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val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
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val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->id, port);
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val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
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I915_WRITE(DPCLKA_CFGCR0, val);
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/*
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@ -2267,7 +2267,7 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder,
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val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
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DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
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val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->id, port) |
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val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) |
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DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
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I915_WRITE(DPLL_CTRL2, val);
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@ -291,19 +291,19 @@ intel_reference_shared_dpll(struct intel_shared_dpll *pll,
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{
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struct intel_shared_dpll_state *shared_dpll;
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struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
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enum intel_dpll_id i = pll->id;
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const enum intel_dpll_id id = pll->info->id;
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shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
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if (shared_dpll[i].crtc_mask == 0)
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shared_dpll[i].hw_state =
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if (shared_dpll[id].crtc_mask == 0)
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shared_dpll[id].hw_state =
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crtc_state->dpll_hw_state;
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crtc_state->shared_dpll = pll;
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DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->info->name,
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pipe_name(crtc->pipe));
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shared_dpll[pll->id].crtc_mask |= 1 << crtc->pipe;
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shared_dpll[id].crtc_mask |= 1 << crtc->pipe;
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}
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/**
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@ -343,15 +343,16 @@ static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
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struct intel_shared_dpll *pll,
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struct intel_dpll_hw_state *hw_state)
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{
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const enum intel_dpll_id id = pll->info->id;
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uint32_t val;
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if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS))
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return false;
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val = I915_READ(PCH_DPLL(pll->id));
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val = I915_READ(PCH_DPLL(id));
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hw_state->dpll = val;
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hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
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hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
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hw_state->fp0 = I915_READ(PCH_FP0(id));
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hw_state->fp1 = I915_READ(PCH_FP1(id));
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intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
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@ -361,8 +362,10 @@ static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
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static void ibx_pch_dpll_prepare(struct drm_i915_private *dev_priv,
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struct intel_shared_dpll *pll)
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{
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I915_WRITE(PCH_FP0(pll->id), pll->state.hw_state.fp0);
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I915_WRITE(PCH_FP1(pll->id), pll->state.hw_state.fp1);
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const enum intel_dpll_id id = pll->info->id;
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I915_WRITE(PCH_FP0(id), pll->state.hw_state.fp0);
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I915_WRITE(PCH_FP1(id), pll->state.hw_state.fp1);
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}
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static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
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@ -381,13 +384,15 @@ static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
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static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
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struct intel_shared_dpll *pll)
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{
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const enum intel_dpll_id id = pll->info->id;
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/* PCH refclock must be enabled first */
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ibx_assert_pch_refclk_enabled(dev_priv);
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I915_WRITE(PCH_DPLL(pll->id), pll->state.hw_state.dpll);
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I915_WRITE(PCH_DPLL(id), pll->state.hw_state.dpll);
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/* Wait for the clocks to stabilize. */
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POSTING_READ(PCH_DPLL(pll->id));
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POSTING_READ(PCH_DPLL(id));
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udelay(150);
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/* The pixel multiplier can only be updated once the
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@ -395,14 +400,15 @@ static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
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*
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* So write it again.
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*/
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I915_WRITE(PCH_DPLL(pll->id), pll->state.hw_state.dpll);
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POSTING_READ(PCH_DPLL(pll->id));
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I915_WRITE(PCH_DPLL(id), pll->state.hw_state.dpll);
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POSTING_READ(PCH_DPLL(id));
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udelay(200);
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}
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static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
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struct intel_shared_dpll *pll)
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{
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const enum intel_dpll_id id = pll->info->id;
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struct drm_device *dev = &dev_priv->drm;
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struct intel_crtc *crtc;
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@ -412,8 +418,8 @@ static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
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assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
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}
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I915_WRITE(PCH_DPLL(pll->id), 0);
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POSTING_READ(PCH_DPLL(pll->id));
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I915_WRITE(PCH_DPLL(id), 0);
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POSTING_READ(PCH_DPLL(id));
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udelay(200);
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}
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@ -469,8 +475,10 @@ static const struct intel_shared_dpll_funcs ibx_pch_dpll_funcs = {
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static void hsw_ddi_wrpll_enable(struct drm_i915_private *dev_priv,
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struct intel_shared_dpll *pll)
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{
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I915_WRITE(WRPLL_CTL(pll->id), pll->state.hw_state.wrpll);
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POSTING_READ(WRPLL_CTL(pll->id));
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const enum intel_dpll_id id = pll->info->id;
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I915_WRITE(WRPLL_CTL(id), pll->state.hw_state.wrpll);
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POSTING_READ(WRPLL_CTL(id));
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udelay(20);
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}
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@ -485,11 +493,12 @@ static void hsw_ddi_spll_enable(struct drm_i915_private *dev_priv,
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static void hsw_ddi_wrpll_disable(struct drm_i915_private *dev_priv,
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struct intel_shared_dpll *pll)
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{
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const enum intel_dpll_id id = pll->info->id;
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uint32_t val;
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val = I915_READ(WRPLL_CTL(pll->id));
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I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE);
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POSTING_READ(WRPLL_CTL(pll->id));
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val = I915_READ(WRPLL_CTL(id));
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I915_WRITE(WRPLL_CTL(id), val & ~WRPLL_PLL_ENABLE);
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POSTING_READ(WRPLL_CTL(id));
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}
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static void hsw_ddi_spll_disable(struct drm_i915_private *dev_priv,
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@ -506,12 +515,13 @@ static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private *dev_priv,
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struct intel_shared_dpll *pll,
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struct intel_dpll_hw_state *hw_state)
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{
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const enum intel_dpll_id id = pll->info->id;
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uint32_t val;
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if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS))
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return false;
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val = I915_READ(WRPLL_CTL(pll->id));
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val = I915_READ(WRPLL_CTL(id));
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hw_state->wrpll = val;
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intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
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@ -917,13 +927,15 @@ static const struct skl_dpll_regs skl_dpll_regs[4] = {
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static void skl_ddi_pll_write_ctrl1(struct drm_i915_private *dev_priv,
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struct intel_shared_dpll *pll)
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{
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const enum intel_dpll_id id = pll->info->id;
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uint32_t val;
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val = I915_READ(DPLL_CTRL1);
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val &= ~(DPLL_CTRL1_HDMI_MODE(pll->id) | DPLL_CTRL1_SSC(pll->id) |
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DPLL_CTRL1_LINK_RATE_MASK(pll->id));
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val |= pll->state.hw_state.ctrl1 << (pll->id * 6);
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val &= ~(DPLL_CTRL1_HDMI_MODE(id) |
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DPLL_CTRL1_SSC(id) |
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DPLL_CTRL1_LINK_RATE_MASK(id));
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val |= pll->state.hw_state.ctrl1 << (id * 6);
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I915_WRITE(DPLL_CTRL1, val);
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POSTING_READ(DPLL_CTRL1);
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@ -933,24 +945,25 @@ static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv,
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struct intel_shared_dpll *pll)
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{
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const struct skl_dpll_regs *regs = skl_dpll_regs;
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const enum intel_dpll_id id = pll->info->id;
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skl_ddi_pll_write_ctrl1(dev_priv, pll);
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I915_WRITE(regs[pll->id].cfgcr1, pll->state.hw_state.cfgcr1);
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I915_WRITE(regs[pll->id].cfgcr2, pll->state.hw_state.cfgcr2);
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POSTING_READ(regs[pll->id].cfgcr1);
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POSTING_READ(regs[pll->id].cfgcr2);
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I915_WRITE(regs[id].cfgcr1, pll->state.hw_state.cfgcr1);
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I915_WRITE(regs[id].cfgcr2, pll->state.hw_state.cfgcr2);
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POSTING_READ(regs[id].cfgcr1);
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POSTING_READ(regs[id].cfgcr2);
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/* the enable bit is always bit 31 */
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I915_WRITE(regs[pll->id].ctl,
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I915_READ(regs[pll->id].ctl) | LCPLL_PLL_ENABLE);
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I915_WRITE(regs[id].ctl,
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I915_READ(regs[id].ctl) | LCPLL_PLL_ENABLE);
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if (intel_wait_for_register(dev_priv,
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DPLL_STATUS,
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DPLL_LOCK(pll->id),
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DPLL_LOCK(pll->id),
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DPLL_LOCK(id),
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DPLL_LOCK(id),
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5))
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DRM_ERROR("DPLL %d not locked\n", pll->id);
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DRM_ERROR("DPLL %d not locked\n", id);
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}
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static void skl_ddi_dpll0_enable(struct drm_i915_private *dev_priv,
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@ -963,11 +976,12 @@ static void skl_ddi_pll_disable(struct drm_i915_private *dev_priv,
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struct intel_shared_dpll *pll)
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{
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const struct skl_dpll_regs *regs = skl_dpll_regs;
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const enum intel_dpll_id id = pll->info->id;
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/* the enable bit is always bit 31 */
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I915_WRITE(regs[pll->id].ctl,
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I915_READ(regs[pll->id].ctl) & ~LCPLL_PLL_ENABLE);
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POSTING_READ(regs[pll->id].ctl);
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I915_WRITE(regs[id].ctl,
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I915_READ(regs[id].ctl) & ~LCPLL_PLL_ENABLE);
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POSTING_READ(regs[id].ctl);
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}
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static void skl_ddi_dpll0_disable(struct drm_i915_private *dev_priv,
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@ -981,6 +995,7 @@ static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
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{
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uint32_t val;
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const struct skl_dpll_regs *regs = skl_dpll_regs;
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const enum intel_dpll_id id = pll->info->id;
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bool ret;
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if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS))
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@ -988,17 +1003,17 @@ static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
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ret = false;
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val = I915_READ(regs[pll->id].ctl);
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val = I915_READ(regs[id].ctl);
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if (!(val & LCPLL_PLL_ENABLE))
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goto out;
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val = I915_READ(DPLL_CTRL1);
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hw_state->ctrl1 = (val >> (pll->id * 6)) & 0x3f;
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hw_state->ctrl1 = (val >> (id * 6)) & 0x3f;
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/* avoid reading back stale values if HDMI mode is not enabled */
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if (val & DPLL_CTRL1_HDMI_MODE(pll->id)) {
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hw_state->cfgcr1 = I915_READ(regs[pll->id].cfgcr1);
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hw_state->cfgcr2 = I915_READ(regs[pll->id].cfgcr2);
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if (val & DPLL_CTRL1_HDMI_MODE(id)) {
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hw_state->cfgcr1 = I915_READ(regs[id].cfgcr1);
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hw_state->cfgcr2 = I915_READ(regs[id].cfgcr2);
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}
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ret = true;
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@ -1014,6 +1029,7 @@ static bool skl_ddi_dpll0_get_hw_state(struct drm_i915_private *dev_priv,
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{
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uint32_t val;
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const struct skl_dpll_regs *regs = skl_dpll_regs;
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const enum intel_dpll_id id = pll->info->id;
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bool ret;
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if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS))
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@ -1022,12 +1038,12 @@ static bool skl_ddi_dpll0_get_hw_state(struct drm_i915_private *dev_priv,
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ret = false;
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/* DPLL0 is always enabled since it drives CDCLK */
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val = I915_READ(regs[pll->id].ctl);
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val = I915_READ(regs[id].ctl);
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if (WARN_ON(!(val & LCPLL_PLL_ENABLE)))
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goto out;
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val = I915_READ(DPLL_CTRL1);
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hw_state->ctrl1 = (val >> (pll->id * 6)) & 0x3f;
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hw_state->ctrl1 = (val >> (id * 6)) & 0x3f;
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ret = true;
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@ -1427,7 +1443,7 @@ static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
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struct intel_shared_dpll *pll)
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{
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uint32_t temp;
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enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
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enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
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enum dpio_phy phy;
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enum dpio_channel ch;
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@ -1546,7 +1562,7 @@ static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
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static void bxt_ddi_pll_disable(struct drm_i915_private *dev_priv,
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struct intel_shared_dpll *pll)
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{
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enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
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enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
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uint32_t temp;
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temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
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@ -1569,7 +1585,7 @@ static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
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struct intel_shared_dpll *pll,
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struct intel_dpll_hw_state *hw_state)
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{
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enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
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enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
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uint32_t val;
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bool ret;
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enum dpio_phy phy;
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@ -1949,38 +1965,39 @@ static const struct intel_dpll_mgr bxt_pll_mgr = {
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static void cnl_ddi_pll_enable(struct drm_i915_private *dev_priv,
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struct intel_shared_dpll *pll)
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{
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const enum intel_dpll_id id = pll->info->id;
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uint32_t val;
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/* 1. Enable DPLL power in DPLL_ENABLE. */
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val = I915_READ(CNL_DPLL_ENABLE(pll->id));
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val = I915_READ(CNL_DPLL_ENABLE(id));
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val |= PLL_POWER_ENABLE;
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I915_WRITE(CNL_DPLL_ENABLE(pll->id), val);
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I915_WRITE(CNL_DPLL_ENABLE(id), val);
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/* 2. Wait for DPLL power state enabled in DPLL_ENABLE. */
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if (intel_wait_for_register(dev_priv,
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CNL_DPLL_ENABLE(pll->id),
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CNL_DPLL_ENABLE(id),
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PLL_POWER_STATE,
|
||||
PLL_POWER_STATE,
|
||||
5))
|
||||
DRM_ERROR("PLL %d Power not enabled\n", pll->id);
|
||||
DRM_ERROR("PLL %d Power not enabled\n", id);
|
||||
|
||||
/*
|
||||
* 3. Configure DPLL_CFGCR0 to set SSC enable/disable,
|
||||
* select DP mode, and set DP link rate.
|
||||
*/
|
||||
val = pll->state.hw_state.cfgcr0;
|
||||
I915_WRITE(CNL_DPLL_CFGCR0(pll->id), val);
|
||||
I915_WRITE(CNL_DPLL_CFGCR0(id), val);
|
||||
|
||||
/* 4. Reab back to ensure writes completed */
|
||||
POSTING_READ(CNL_DPLL_CFGCR0(pll->id));
|
||||
POSTING_READ(CNL_DPLL_CFGCR0(id));
|
||||
|
||||
/* 3. Configure DPLL_CFGCR0 */
|
||||
/* Avoid touch CFGCR1 if HDMI mode is not enabled */
|
||||
if (pll->state.hw_state.cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {
|
||||
val = pll->state.hw_state.cfgcr1;
|
||||
I915_WRITE(CNL_DPLL_CFGCR1(pll->id), val);
|
||||
I915_WRITE(CNL_DPLL_CFGCR1(id), val);
|
||||
/* 4. Reab back to ensure writes completed */
|
||||
POSTING_READ(CNL_DPLL_CFGCR1(pll->id));
|
||||
POSTING_READ(CNL_DPLL_CFGCR1(id));
|
||||
}
|
||||
|
||||
/*
|
||||
@ -1993,17 +2010,17 @@ static void cnl_ddi_pll_enable(struct drm_i915_private *dev_priv,
|
||||
*/
|
||||
|
||||
/* 6. Enable DPLL in DPLL_ENABLE. */
|
||||
val = I915_READ(CNL_DPLL_ENABLE(pll->id));
|
||||
val = I915_READ(CNL_DPLL_ENABLE(id));
|
||||
val |= PLL_ENABLE;
|
||||
I915_WRITE(CNL_DPLL_ENABLE(pll->id), val);
|
||||
I915_WRITE(CNL_DPLL_ENABLE(id), val);
|
||||
|
||||
/* 7. Wait for PLL lock status in DPLL_ENABLE. */
|
||||
if (intel_wait_for_register(dev_priv,
|
||||
CNL_DPLL_ENABLE(pll->id),
|
||||
CNL_DPLL_ENABLE(id),
|
||||
PLL_LOCK,
|
||||
PLL_LOCK,
|
||||
5))
|
||||
DRM_ERROR("PLL %d not locked\n", pll->id);
|
||||
DRM_ERROR("PLL %d not locked\n", id);
|
||||
|
||||
/*
|
||||
* 8. If the frequency will result in a change to the voltage
|
||||
@ -2023,6 +2040,7 @@ static void cnl_ddi_pll_enable(struct drm_i915_private *dev_priv,
|
||||
static void cnl_ddi_pll_disable(struct drm_i915_private *dev_priv,
|
||||
struct intel_shared_dpll *pll)
|
||||
{
|
||||
const enum intel_dpll_id id = pll->info->id;
|
||||
uint32_t val;
|
||||
|
||||
/*
|
||||
@ -2040,17 +2058,17 @@ static void cnl_ddi_pll_disable(struct drm_i915_private *dev_priv,
|
||||
*/
|
||||
|
||||
/* 3. Disable DPLL through DPLL_ENABLE. */
|
||||
val = I915_READ(CNL_DPLL_ENABLE(pll->id));
|
||||
val = I915_READ(CNL_DPLL_ENABLE(id));
|
||||
val &= ~PLL_ENABLE;
|
||||
I915_WRITE(CNL_DPLL_ENABLE(pll->id), val);
|
||||
I915_WRITE(CNL_DPLL_ENABLE(id), val);
|
||||
|
||||
/* 4. Wait for PLL not locked status in DPLL_ENABLE. */
|
||||
if (intel_wait_for_register(dev_priv,
|
||||
CNL_DPLL_ENABLE(pll->id),
|
||||
CNL_DPLL_ENABLE(id),
|
||||
PLL_LOCK,
|
||||
0,
|
||||
5))
|
||||
DRM_ERROR("PLL %d locked\n", pll->id);
|
||||
DRM_ERROR("PLL %d locked\n", id);
|
||||
|
||||
/*
|
||||
* 5. If the frequency will result in a change to the voltage
|
||||
@ -2062,23 +2080,24 @@ static void cnl_ddi_pll_disable(struct drm_i915_private *dev_priv,
|
||||
*/
|
||||
|
||||
/* 6. Disable DPLL power in DPLL_ENABLE. */
|
||||
val = I915_READ(CNL_DPLL_ENABLE(pll->id));
|
||||
val = I915_READ(CNL_DPLL_ENABLE(id));
|
||||
val &= ~PLL_POWER_ENABLE;
|
||||
I915_WRITE(CNL_DPLL_ENABLE(pll->id), val);
|
||||
I915_WRITE(CNL_DPLL_ENABLE(id), val);
|
||||
|
||||
/* 7. Wait for DPLL power state disabled in DPLL_ENABLE. */
|
||||
if (intel_wait_for_register(dev_priv,
|
||||
CNL_DPLL_ENABLE(pll->id),
|
||||
CNL_DPLL_ENABLE(id),
|
||||
PLL_POWER_STATE,
|
||||
0,
|
||||
5))
|
||||
DRM_ERROR("PLL %d Power not disabled\n", pll->id);
|
||||
DRM_ERROR("PLL %d Power not disabled\n", id);
|
||||
}
|
||||
|
||||
static bool cnl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
|
||||
struct intel_shared_dpll *pll,
|
||||
struct intel_dpll_hw_state *hw_state)
|
||||
{
|
||||
const enum intel_dpll_id id = pll->info->id;
|
||||
uint32_t val;
|
||||
bool ret;
|
||||
|
||||
@ -2087,16 +2106,16 @@ static bool cnl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
|
||||
|
||||
ret = false;
|
||||
|
||||
val = I915_READ(CNL_DPLL_ENABLE(pll->id));
|
||||
val = I915_READ(CNL_DPLL_ENABLE(id));
|
||||
if (!(val & PLL_ENABLE))
|
||||
goto out;
|
||||
|
||||
val = I915_READ(CNL_DPLL_CFGCR0(pll->id));
|
||||
val = I915_READ(CNL_DPLL_CFGCR0(id));
|
||||
hw_state->cfgcr0 = val;
|
||||
|
||||
/* avoid reading back stale values if HDMI mode is not enabled */
|
||||
if (val & DPLL_CFGCR0_HDMI_MODE) {
|
||||
hw_state->cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(pll->id));
|
||||
hw_state->cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(id));
|
||||
}
|
||||
ret = true;
|
||||
|
||||
@ -2415,7 +2434,6 @@ void intel_shared_dpll_init(struct drm_device *dev)
|
||||
WARN_ON(i != dpll_info[i].id);
|
||||
dev_priv->shared_dplls[i].info = &dpll_info[i];
|
||||
|
||||
dev_priv->shared_dplls[i].id = dpll_info[i].id;
|
||||
dev_priv->shared_dplls[i].flags = dpll_info[i].flags;
|
||||
}
|
||||
|
||||
@ -2476,7 +2494,7 @@ void intel_release_shared_dpll(struct intel_shared_dpll *dpll,
|
||||
struct intel_shared_dpll_state *shared_dpll_state;
|
||||
|
||||
shared_dpll_state = intel_atomic_get_shared_dpll_state(state);
|
||||
shared_dpll_state[dpll->id].crtc_mask &= ~(1 << crtc->pipe);
|
||||
shared_dpll_state[dpll->info->id].crtc_mask &= ~(1 << crtc->pipe);
|
||||
}
|
||||
|
||||
/**
|
||||
|
||||
@ -213,6 +213,10 @@ struct dpll_info {
|
||||
* @name: DPLL name; used for logging
|
||||
*/
|
||||
const char *name;
|
||||
/**
|
||||
* @id: unique indentifier for this DPLL; should match the index in the
|
||||
* dev_priv->shared_dplls array
|
||||
*/
|
||||
const int id;
|
||||
/**
|
||||
* @funcs: platform specific hooks
|
||||
@ -243,12 +247,6 @@ struct intel_shared_dpll {
|
||||
*/
|
||||
bool on;
|
||||
|
||||
/**
|
||||
* @id: unique indentifier for this DPLL; should match the index in the
|
||||
* dev_priv->shared_dplls array
|
||||
*/
|
||||
enum intel_dpll_id id;
|
||||
|
||||
/**
|
||||
* @info: platform specific info
|
||||
*/
|
||||
|
||||
Loading…
Reference in New Issue
Block a user