forked from Minki/linux
clk: samsung: Define a common samsung_clk_register_pll()
This patch defines a common samsung_clk_register_pll() Since pll2550 & pll35xx and pll2650 & pll36xx have exactly same clk ops implementation, added pll2550 and pll2650 also. Signed-off-by: Yadwinder Singh Brar <yadi.brar@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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079dbead49
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@ -17,6 +17,7 @@ struct samsung_clk_pll {
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struct clk_hw hw;
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struct clk_hw hw;
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void __iomem *lock_reg;
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void __iomem *lock_reg;
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void __iomem *con_reg;
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void __iomem *con_reg;
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enum samsung_pll_type type;
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};
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};
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#define to_clk_pll(_hw) container_of(_hw, struct samsung_clk_pll, hw)
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#define to_clk_pll(_hw) container_of(_hw, struct samsung_clk_pll, hw)
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@ -412,3 +413,72 @@ struct clk * __init samsung_clk_register_pll2550x(const char *name,
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return clk;
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return clk;
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}
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}
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static void __init _samsung_clk_register_pll(struct samsung_pll_clock *pll_clk,
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void __iomem *base)
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{
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struct samsung_clk_pll *pll;
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struct clk *clk;
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struct clk_init_data init;
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int ret;
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pll = kzalloc(sizeof(*pll), GFP_KERNEL);
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if (!pll) {
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pr_err("%s: could not allocate pll clk %s\n",
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__func__, pll_clk->name);
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return;
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}
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init.name = pll_clk->name;
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init.flags = pll_clk->flags;
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init.parent_names = &pll_clk->parent_name;
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init.num_parents = 1;
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switch (pll_clk->type) {
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/* clk_ops for 35xx and 2550 are similar */
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case pll_35xx:
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case pll_2550:
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init.ops = &samsung_pll35xx_clk_ops;
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break;
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/* clk_ops for 36xx and 2650 are similar */
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case pll_36xx:
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case pll_2650:
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init.ops = &samsung_pll36xx_clk_ops;
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break;
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default:
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pr_warn("%s: Unknown pll type for pll clk %s\n",
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__func__, pll_clk->name);
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}
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pll->hw.init = &init;
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pll->type = pll_clk->type;
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pll->lock_reg = base + pll_clk->lock_offset;
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pll->con_reg = base + pll_clk->con_offset;
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clk = clk_register(NULL, &pll->hw);
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if (IS_ERR(clk)) {
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pr_err("%s: failed to register pll clock %s : %ld\n",
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__func__, pll_clk->name, PTR_ERR(clk));
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kfree(pll);
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return;
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}
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samsung_clk_add_lookup(clk, pll_clk->id);
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if (!pll_clk->alias)
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return;
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ret = clk_register_clkdev(clk, pll_clk->alias, pll_clk->dev_name);
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if (ret)
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pr_err("%s: failed to register lookup for %s : %d",
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__func__, pll_clk->name, ret);
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}
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void __init samsung_clk_register_pll(struct samsung_pll_clock *pll_list,
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unsigned int nr_pll, void __iomem *base)
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{
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int cnt;
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for (cnt = 0; cnt < nr_pll; cnt++)
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_samsung_clk_register_pll(&pll_list[cnt], base);
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}
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@ -12,6 +12,13 @@
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#ifndef __SAMSUNG_CLK_PLL_H
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#ifndef __SAMSUNG_CLK_PLL_H
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#define __SAMSUNG_CLK_PLL_H
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#define __SAMSUNG_CLK_PLL_H
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enum samsung_pll_type {
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pll_35xx,
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pll_36xx,
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pll_2550,
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pll_2650,
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};
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enum pll45xx_type {
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enum pll45xx_type {
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pll_4500,
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pll_4500,
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pll_4502,
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pll_4502,
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@ -19,6 +19,7 @@
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#include <linux/clk-provider.h>
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#include <linux/clk-provider.h>
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#include <linux/of.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_address.h>
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#include "clk-pll.h"
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/**
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/**
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* struct samsung_clock_alias: information about mux clock
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* struct samsung_clock_alias: information about mux clock
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@ -261,6 +262,51 @@ struct samsung_clk_reg_dump {
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u32 value;
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u32 value;
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};
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};
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/**
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* struct samsung_pll_clock: information about pll clock
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* @id: platform specific id of the clock.
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* @dev_name: name of the device to which this clock belongs.
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* @name: name of this pll clock.
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* @parent_name: name of the parent clock.
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* @flags: optional flags for basic clock.
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* @con_offset: offset of the register for configuring the PLL.
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* @lock_offset: offset of the register for locking the PLL.
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* @type: Type of PLL to be registered.
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* @alias: optional clock alias name to be assigned to this clock.
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*/
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struct samsung_pll_clock {
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unsigned int id;
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const char *dev_name;
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const char *name;
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const char *parent_name;
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unsigned long flags;
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int con_offset;
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int lock_offset;
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enum samsung_pll_type type;
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const char *alias;
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};
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#define __PLL(_typ, _id, _dname, _name, _pname, _flags, _lock, _con, _alias) \
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{ \
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.id = _id, \
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.type = _typ, \
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.dev_name = _dname, \
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.name = _name, \
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.parent_name = _pname, \
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.flags = CLK_GET_RATE_NOCACHE, \
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.con_offset = _con, \
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.lock_offset = _lock, \
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.alias = _alias, \
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}
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#define PLL(_typ, _id, _name, _pname, _lock, _con) \
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__PLL(_typ, _id, NULL, _name, _pname, CLK_GET_RATE_NOCACHE, \
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_lock, _con, NULL)
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#define PLL_A(_typ, _id, _name, _pname, _lock, _con, _alias) \
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__PLL(_typ, _id, NULL, _name, _pname, CLK_GET_RATE_NOCACHE, \
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_lock, _con, _alias)
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extern void __init samsung_clk_init(struct device_node *np, void __iomem *base,
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extern void __init samsung_clk_init(struct device_node *np, void __iomem *base,
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unsigned long nr_clks, unsigned long *rdump,
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unsigned long nr_clks, unsigned long *rdump,
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unsigned long nr_rdump, unsigned long *soc_rdump,
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unsigned long nr_rdump, unsigned long *soc_rdump,
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@ -284,6 +330,8 @@ extern void __init samsung_clk_register_div(struct samsung_div_clock *clk_list,
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unsigned int nr_clk);
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unsigned int nr_clk);
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extern void __init samsung_clk_register_gate(
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extern void __init samsung_clk_register_gate(
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struct samsung_gate_clock *clk_list, unsigned int nr_clk);
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struct samsung_gate_clock *clk_list, unsigned int nr_clk);
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extern void __init samsung_clk_register_pll(struct samsung_pll_clock *pll_list,
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unsigned int nr_clk, void __iomem *base);
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extern unsigned long _get_rate(const char *clk_name);
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extern unsigned long _get_rate(const char *clk_name);
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