forked from Minki/linux
[PATCH] ppc32: 8xx commproc avoid direct pte manipulation, use dma coherent API instead
Touching the pte directly causes the 8Mbyte TLB entry to be invalidated. This has been fixed in v2.4 for ages. Signed-off-by: Marcelo Tosatti <marcelo.tosatti@cyclades.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
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@ -39,8 +39,6 @@
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#include <asm/tlbflush.h>
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#include <asm/rheap.h>
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extern int get_pteptr(struct mm_struct *mm, unsigned long addr, pte_t **ptep);
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static void m8xx_cpm_dpinit(void);
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static uint host_buffer; /* One page of host buffer */
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static uint host_end; /* end + 1 */
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@ -108,14 +106,11 @@ struct hw_interrupt_type cpm_pic = {
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.end = cpm_eoi,
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};
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extern void flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr);
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void
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m8xx_cpm_reset(uint bootpage)
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m8xx_cpm_reset(void)
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{
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volatile immap_t *imp;
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volatile cpm8xx_t *commproc;
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pte_t *pte;
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imp = (immap_t *)IMAP_ADDR;
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commproc = (cpm8xx_t *)&imp->im_cpm;
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@ -143,17 +138,6 @@ m8xx_cpm_reset(uint bootpage)
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/* Reclaim the DP memory for our use. */
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m8xx_cpm_dpinit();
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/* get the PTE for the bootpage */
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if (!get_pteptr(&init_mm, bootpage, &pte))
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panic("get_pteptr failed\n");
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/* and make it uncachable */
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pte_val(*pte) |= _PAGE_NO_CACHE;
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_tlbie(bootpage);
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host_buffer = bootpage;
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host_end = host_buffer + PAGE_SIZE;
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/* Tell everyone where the comm processor resides.
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*/
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cpmp = (cpm8xx_t *)commproc;
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@ -57,7 +57,7 @@ unsigned char __res[sizeof(bd_t)];
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extern void m8xx_ide_init(void);
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extern unsigned long find_available_memory(void);
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extern void m8xx_cpm_reset(uint cpm_page);
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extern void m8xx_cpm_reset();
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extern void m8xx_wdt_handler_install(bd_t *bp);
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extern void rpxfb_alloc_pages(void);
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extern void cpm_interrupt_init(void);
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@ -70,13 +70,9 @@ board_init(void)
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void __init
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m8xx_setup_arch(void)
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{
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int cpm_page;
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cpm_page = (int) alloc_bootmem_pages(PAGE_SIZE);
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/* Reset the Communication Processor Module.
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*/
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m8xx_cpm_reset(cpm_page);
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m8xx_cpm_reset();
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#ifdef CONFIG_FB_RPX
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rpxfb_alloc_pages();
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