forked from Minki/linux
MIPS: Alchemy: remove cpu_table.
Remove the cpu_table: - move detection of whether c0_config[OD] is read-only and should be set to fix various chip errata to au1000 headers. - move detection of write-only sys_cpupll to au1000 headers. - remove the BCLK switching code: Activation of this features should be left to the boards using the chips since it also affects external devices tied to BCLK, and only the board designers know whether it is safe to enable. Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> delete mode 100644 arch/mips/alchemy/common/cputable.c
This commit is contained in:
Manuel Lauss
Ralf Baechle
parent
1820ec1d2b
commit
074cf65670
@ -7,7 +7,7 @@
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obj-y += prom.o irq.o puts.o time.o reset.o \
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clocks.o platform.o power.o setup.o \
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sleeper.o cputable.o dma.o dbdma.o gpio.o
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sleeper.o dma.o dbdma.o gpio.o
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obj-$(CONFIG_PCI) += pci.o
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@ -1,52 +0,0 @@
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/*
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* arch/mips/au1000/common/cputable.c
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*
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* Copyright (C) 2004 Dan Malek (dan@embeddededge.com)
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* Copied from PowerPC and updated for Alchemy Au1xxx processors.
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*
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* Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <asm/mach-au1x00/au1000.h>
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struct cpu_spec *cur_cpu_spec[NR_CPUS];
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/* With some thought, we can probably use the mask to reduce the
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* size of the table.
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*/
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struct cpu_spec cpu_specs[] = {
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{ 0xffffffff, 0x00030100, "Au1000 DA", 1, 0, 1 },
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{ 0xffffffff, 0x00030201, "Au1000 HA", 1, 0, 1 },
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{ 0xffffffff, 0x00030202, "Au1000 HB", 1, 0, 1 },
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{ 0xffffffff, 0x00030203, "Au1000 HC", 1, 1, 0 },
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{ 0xffffffff, 0x00030204, "Au1000 HD", 1, 1, 0 },
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{ 0xffffffff, 0x01030200, "Au1500 AB", 1, 1, 0 },
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{ 0xffffffff, 0x01030201, "Au1500 AC", 0, 1, 0 },
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{ 0xffffffff, 0x01030202, "Au1500 AD", 0, 1, 0 },
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{ 0xffffffff, 0x02030200, "Au1100 AB", 1, 1, 0 },
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{ 0xffffffff, 0x02030201, "Au1100 BA", 1, 1, 0 },
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{ 0xffffffff, 0x02030202, "Au1100 BC", 1, 1, 0 },
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{ 0xffffffff, 0x02030203, "Au1100 BD", 0, 1, 0 },
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{ 0xffffffff, 0x02030204, "Au1100 BE", 0, 1, 0 },
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{ 0xffffffff, 0x03030200, "Au1550 AA", 0, 1, 0 },
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{ 0xffffffff, 0x04030200, "Au1200 AB", 0, 0, 0 },
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{ 0xffffffff, 0x04030201, "Au1200 AC", 1, 0, 0 },
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{ 0x00000000, 0x00000000, "Unknown Au1xxx", 1, 0, 0 }
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};
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void set_cpuspec(void)
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{
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struct cpu_spec *sp;
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u32 prid;
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prid = read_c0_prid();
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sp = cpu_specs;
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while ((prid & sp->prid_mask) != sp->prid_value)
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sp++;
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cur_cpu_spec[0] = sp;
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}
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@ -44,37 +44,13 @@ extern void set_cpuspec(void);
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void __init plat_mem_setup(void)
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{
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struct cpu_spec *sp;
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unsigned long prid, cpufreq, bclk;
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set_cpuspec();
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sp = cur_cpu_spec[0];
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_machine_restart = au1000_restart;
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_machine_halt = au1000_halt;
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pm_power_off = au1000_power_off;
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board_setup(); /* board specific setup */
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prid = read_c0_prid();
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if (sp->cpu_pll_wo)
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#ifdef CONFIG_SOC_AU1000_FREQUENCY
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cpufreq = CONFIG_SOC_AU1000_FREQUENCY / 1000000;
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#else
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cpufreq = 396;
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#endif
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else
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cpufreq = (au_readl(SYS_CPUPLL) & 0x3F) * 12;
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printk(KERN_INFO "(PRID %08lx) @ %ld MHz\n", prid, cpufreq);
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if (sp->cpu_bclk) {
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/* Enable BCLK switching */
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bclk = au_readl(SYS_POWERCTRL);
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au_writel(bclk | 0x60, SYS_POWERCTRL);
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printk(KERN_INFO "BCLK switching enabled!\n");
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}
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if (sp->cpu_od)
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if (au1xxx_cpu_needs_config_od())
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/* Various early Au1xx0 errata corrected by this */
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set_c0_config(1 << 19); /* Set Config[OD] */
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else
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@ -198,7 +198,7 @@ unsigned long calc_clock(void)
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* silicon versions of Au1000 are not sold by AMD, we don't bend
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* over backwards trying to determine the frequency.
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*/
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if (cur_cpu_spec[0]->cpu_pll_wo)
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if (au1xxx_cpu_has_pll_wo())
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#ifdef CONFIG_SOC_AU1000_FREQUENCY
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cpu_speed = CONFIG_SOC_AU1000_FREQUENCY;
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#else
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@ -221,7 +221,7 @@ void __init plat_time_init(void)
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est_freq += 5000; /* round */
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est_freq -= est_freq%10000;
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printk(KERN_INFO "CPU frequency %u.%02u MHz\n",
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printk(KERN_INFO "(PRId %08x) @ %u.%02u MHz\n", read_c0_prid(),
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est_freq / 1000000, ((est_freq % 1000000) * 100) / 1000000);
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set_au1x00_speed(est_freq);
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@ -91,6 +91,44 @@ static inline u32 au_readl(unsigned long reg)
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return *(volatile u32 *)reg;
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}
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/* Early Au1000 have a write-only SYS_CPUPLL register. */
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static inline int au1xxx_cpu_has_pll_wo(void)
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{
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switch (read_c0_prid()) {
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case 0x00030100: /* Au1000 DA */
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case 0x00030201: /* Au1000 HA */
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case 0x00030202: /* Au1000 HB */
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return 1;
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}
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return 0;
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}
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/* does CPU need CONFIG[OD] set to fix tons of errata? */
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static inline int au1xxx_cpu_needs_config_od(void)
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{
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/*
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* c0_config.od (bit 19) was write only (and read as 0) on the
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* early revisions of Alchemy SOCs. It disables the bus trans-
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* action overlapping and needs to be set to fix various errata.
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*/
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switch (read_c0_prid()) {
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case 0x00030100: /* Au1000 DA */
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case 0x00030201: /* Au1000 HA */
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case 0x00030202: /* Au1000 HB */
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case 0x01030200: /* Au1500 AB */
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/*
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* Au1100/Au1200 errata actually keep silence about this bit,
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* so we set it just in case for those revisions that require
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* it to be set according to the (now gone) cpu_table.
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*/
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case 0x02030200: /* Au1100 AB */
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case 0x02030201: /* Au1100 BA */
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case 0x02030202: /* Au1100 BC */
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case 0x04030201: /* Au1200 AC */
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return 1;
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}
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return 0;
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}
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/* arch/mips/au1000/common/clocks.c */
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extern void set_au1x00_speed(unsigned int new_freq);
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@ -1739,24 +1777,4 @@ static AU1X00_SYS * const sys = (AU1X00_SYS *)SYS_BASE;
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#endif
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/*
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* Processor information based on PRID.
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* Copied from PowerPC.
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*/
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#ifndef _LANGUAGE_ASSEMBLY
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struct cpu_spec {
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/* CPU is matched via (PRID & prid_mask) == prid_value */
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unsigned int prid_mask;
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unsigned int prid_value;
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char *cpu_name;
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unsigned char cpu_od; /* Set Config[OD] */
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unsigned char cpu_bclk; /* Enable BCLK switching */
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unsigned char cpu_pll_wo; /* sys_cpupll reg. write-only */
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};
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extern struct cpu_spec cpu_specs[];
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extern struct cpu_spec *cur_cpu_spec[];
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#endif
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#endif
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