forked from Minki/linux
staging: mt7621-pci: use gpio perst instead of builtin behaviour
Some boards seems to ignore the PERST builtin behaviour to properly
perform a pcie line reset. Use gpio PERST behaviour instead which
seems to be more common.
Fixes: bd1a05bd87 ("staging: mt7621-pci: use PERST_N instead of gpio control")
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Sergio Paracuellos
Greg Kroah-Hartman
parent
fdd228cd6d
commit
07420a02b0
@ -17,6 +17,7 @@
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include <linux/gpio/consumer.h>
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#include <linux/iopoll.h>
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#include <linux/module.h>
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#include <linux/of.h>
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@ -35,6 +36,7 @@
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/* sysctl */
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#define MT7621_CHIP_REV_ID 0x0c
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#define MT7621_GPIO_MODE 0x60
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#define CHIP_REV_MT7621_E2 0x0101
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/* MediaTek specific configuration registers */
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@ -81,7 +83,6 @@
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#define PCIE_BAR_ENABLE BIT(0)
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#define PCIE_PORT_INT_EN(x) BIT(20 + (x))
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#define PCIE_PORT_CLK_EN(x) BIT(24 + (x))
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#define PCIE_PORT_PERST(x) BIT(1 + (x))
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#define PCIE_PORT_LINKUP BIT(0)
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#define PCIE_CLK_GEN_EN BIT(31)
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@ -89,6 +90,9 @@
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#define PCIE_CLK_GEN1_DIS GENMASK(30, 24)
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#define PCIE_CLK_GEN1_EN (BIT(27) | BIT(25))
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#define MEMORY_BASE 0x0
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#define PERST_MODE_MASK GENMASK(11, 10)
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#define PERST_MODE_GPIO BIT(10)
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#define PERST_DELAY_US 1000
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/**
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* struct mt7621_pcie_port - PCIe port information
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@ -119,6 +123,7 @@ struct mt7621_pcie_port {
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* @offset: IO / Memory offset
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* @dev: Pointer to PCIe device
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* @ports: pointer to PCIe port information
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* @perst: gpio reset
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* @rst: pointer to pcie reset
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*/
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struct mt7621_pcie {
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@ -132,6 +137,7 @@ struct mt7621_pcie {
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resource_size_t io;
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} offset;
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struct list_head ports;
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struct gpio_desc *perst;
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struct reset_control *rst;
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};
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@ -198,6 +204,23 @@ static void write_config(struct mt7621_pcie *pcie, unsigned int dev,
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pcie_write(pcie, val, RALINK_PCI_CONFIG_DATA);
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}
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static inline void mt7621_perst_gpio_pcie_assert(struct mt7621_pcie *pcie)
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{
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gpiod_set_value(pcie->perst, 0);
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mdelay(PERST_DELAY_US);
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}
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static inline void mt7621_perst_gpio_pcie_deassert(struct mt7621_pcie *pcie)
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{
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gpiod_set_value(pcie->perst, 1);
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mdelay(PERST_DELAY_US);
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}
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static inline bool mt7621_pcie_port_is_linkup(struct mt7621_pcie_port *port)
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{
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return (pcie_port_read(port, RALINK_PCI_STATUS) & PCIE_PORT_LINKUP) != 0;
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}
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static inline void mt7621_control_assert(struct mt7621_pcie_port *port)
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{
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u32 chip_rev_id = rt_sysc_r32(MT7621_CHIP_REV_ID);
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@ -344,6 +367,12 @@ static int mt7621_pcie_parse_dt(struct mt7621_pcie *pcie)
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struct resource regs;
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int err;
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pcie->perst = devm_gpiod_get(dev, "perst", GPIOD_OUT_HIGH);
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if (IS_ERR(pcie->perst)) {
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dev_err(dev, "failed to get gpio perst\n");
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return PTR_ERR(pcie->perst);
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}
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err = of_address_to_resource(node, 0, ®s);
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if (err) {
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dev_err(dev, "missing \"reg\" property\n");
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@ -384,7 +413,6 @@ static int mt7621_pcie_init_port(struct mt7621_pcie_port *port)
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struct mt7621_pcie *pcie = port->pcie;
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struct device *dev = pcie->dev;
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u32 slot = port->slot;
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u32 val = 0;
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int err;
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/*
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@ -393,47 +421,34 @@ static int mt7621_pcie_init_port(struct mt7621_pcie_port *port)
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*/
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mt7621_reset_port(port);
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val = read_config(pcie, slot, PCIE_FTS_NUM);
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dev_info(dev, "Port %d N_FTS = %x\n", slot, (unsigned int)val);
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err = phy_init(port->phy);
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if (err) {
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dev_err(dev, "failed to initialize port%d phy\n", slot);
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goto err_phy_init;
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return err;
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}
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err = phy_power_on(port->phy);
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if (err) {
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dev_err(dev, "failed to power on port%d phy\n", slot);
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goto err_phy_on;
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}
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if ((pcie_port_read(port, RALINK_PCI_STATUS) & PCIE_PORT_LINKUP) == 0) {
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dev_err(dev, "pcie%d no card, disable it (RST & CLK)\n", slot);
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mt7621_control_assert(port);
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port->enabled = false;
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err = -ENODEV;
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goto err_no_link_up;
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return err;
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}
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port->enabled = true;
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return 0;
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err_no_link_up:
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phy_power_off(port->phy);
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err_phy_on:
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phy_exit(port->phy);
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err_phy_init:
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return err;
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}
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static void mt7621_pcie_init_ports(struct mt7621_pcie *pcie)
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{
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struct device *dev = pcie->dev;
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struct mt7621_pcie_port *port, *tmp;
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u32 val = 0;
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int err;
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rt_sysc_m32(PERST_MODE_MASK, PERST_MODE_GPIO, MT7621_GPIO_MODE);
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mt7621_perst_gpio_pcie_assert(pcie);
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list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
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u32 slot = port->slot;
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@ -441,10 +456,29 @@ static void mt7621_pcie_init_ports(struct mt7621_pcie *pcie)
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if (err) {
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dev_err(dev, "Initiating port %d failed\n", slot);
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list_del(&port->list);
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} else {
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val = read_config(pcie, slot, PCIE_FTS_NUM);
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dev_info(dev, "Port %d N_FTS = %x\n", slot,
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(unsigned int)val);
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}
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}
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reset_control_assert(pcie->rst);
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mt7621_perst_gpio_pcie_deassert(pcie);
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list_for_each_entry(port, &pcie->ports, list) {
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u32 slot = port->slot;
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if (!mt7621_pcie_port_is_linkup(port)) {
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dev_err(dev, "pcie%d no card, disable it (RST & CLK)\n",
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slot);
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phy_power_off(port->phy);
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mt7621_control_assert(port);
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port->enabled = false;
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}
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}
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rt_sysc_m32(0x30, 2 << 4, SYSC_REG_SYSTEM_CONFIG1);
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rt_sysc_m32(PCIE_CLK_GEN_EN, PCIE_CLK_GEN_DIS, RALINK_PCIE_CLK_GEN);
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rt_sysc_m32(PCIE_CLK_GEN1_DIS, PCIE_CLK_GEN1_EN, RALINK_PCIE_CLK_GEN1);
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@ -453,30 +487,12 @@ static void mt7621_pcie_init_ports(struct mt7621_pcie *pcie)
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reset_control_deassert(pcie->rst);
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}
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static int mt7621_pcie_enable_port(struct mt7621_pcie_port *port)
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static void mt7621_pcie_enable_port(struct mt7621_pcie_port *port)
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{
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struct mt7621_pcie *pcie = port->pcie;
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u32 slot = port->slot;
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u32 offset = MT7621_PCIE_OFFSET + (slot * MT7621_NEXT_PORT);
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u32 val;
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int err;
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/* assert port PERST_N */
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val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR);
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val |= PCIE_PORT_PERST(slot);
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pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR);
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/* de-assert port PERST_N */
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val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR);
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val &= ~PCIE_PORT_PERST(slot);
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pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR);
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/* 100ms timeout value should be enough for Gen1 training */
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err = readl_poll_timeout(port->base + RALINK_PCI_STATUS,
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val, !!(val & PCIE_PORT_LINKUP),
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20, 100 * USEC_PER_MSEC);
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if (err)
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return -ETIMEDOUT;
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/* enable pcie interrupt */
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val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR);
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@ -492,8 +508,6 @@ static int mt7621_pcie_enable_port(struct mt7621_pcie_port *port)
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/* configure class code and revision ID */
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pcie_write(pcie, PCIE_CLASS_CODE | PCIE_REVISION_ID,
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offset + RALINK_PCI_CLASS);
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return 0;
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}
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static void mt7621_pcie_enable_ports(struct mt7621_pcie *pcie)
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@ -506,11 +520,7 @@ static void mt7621_pcie_enable_ports(struct mt7621_pcie *pcie)
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list_for_each_entry(port, &pcie->ports, list) {
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if (port->enabled) {
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if (mt7621_pcie_enable_port(port)) {
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dev_err(dev, "de-assert port %d PERST_N\n",
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port->slot);
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continue;
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}
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mt7621_pcie_enable_port(port);
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dev_info(dev, "PCIE%d enabled\n", num_slots_enabled);
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num_slots_enabled++;
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}
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