forked from Minki/linux
imx-drm: ipu-v3: more clocking fixes
There's no point in using the clk API for this; we end up having to violate the layering this provides. Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Shawn Guo <shawn.guo@linaro.org> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Russell King
parent
370b181516
commit
0721feeee0
@ -19,9 +19,6 @@
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#include <linux/io.h>
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#include <linux/err.h>
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#include <linux/platform_device.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/clkdev.h>
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#include "imx-ipu-v3.h"
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#include "ipu-prv.h"
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@ -33,10 +30,7 @@ struct ipu_di {
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struct clk *clk_di; /* display input clock */
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struct clk *clk_ipu; /* IPU bus clock */
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struct clk *clk_di_pixel; /* resulting pixel clock */
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struct clk_hw clk_hw_out;
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char *clk_name;
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bool inuse;
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unsigned long clkflags;
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struct ipu_soc *ipu;
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};
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@ -141,130 +135,6 @@ static inline void ipu_di_write(struct ipu_di *di, u32 value, unsigned offset)
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writel(value, di->base + offset);
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}
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static int ipu_di_clk_calc_div(unsigned long inrate, unsigned long outrate)
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{
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u64 tmp = inrate;
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int div;
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tmp *= 16;
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do_div(tmp, outrate);
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div = tmp;
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if (div < 0x10)
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div = 0x10;
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#ifdef WTF_IS_THIS
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/*
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* Freescale has this in their Kernel. It is neither clear what
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* it does nor why it does it
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*/
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if (div & 0x10)
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div &= ~0x7;
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else {
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/* Round up divider if it gets us closer to desired pix clk */
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if ((div & 0xC) == 0xC) {
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div += 0x10;
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div &= ~0xF;
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}
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}
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#endif
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return div;
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}
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static unsigned long clk_di_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct ipu_di *di = container_of(hw, struct ipu_di, clk_hw_out);
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unsigned long outrate;
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u32 div = ipu_di_read(di, DI_BS_CLKGEN0);
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if (div < 0x10)
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div = 0x10;
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outrate = (parent_rate / div) * 16;
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return outrate;
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}
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static long clk_di_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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struct ipu_di *di = container_of(hw, struct ipu_di, clk_hw_out);
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unsigned long outrate;
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int div;
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u32 val;
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div = ipu_di_clk_calc_div(*prate, rate);
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outrate = (*prate / div) * 16;
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val = ipu_di_read(di, DI_GENERAL);
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if (!(val & DI_GEN_DI_CLK_EXT) && outrate > *prate / 2)
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outrate = *prate / 2;
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dev_dbg(di->ipu->dev,
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"%s: inrate: %ld div: 0x%08x outrate: %ld wanted: %ld\n",
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__func__, *prate, div, outrate, rate);
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return outrate;
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}
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static int clk_di_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct ipu_di *di = container_of(hw, struct ipu_di, clk_hw_out);
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int div;
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u32 clkgen0;
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clkgen0 = ipu_di_read(di, DI_BS_CLKGEN0) & ~0xfff;
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div = ipu_di_clk_calc_div(parent_rate, rate);
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ipu_di_write(di, clkgen0 | div, DI_BS_CLKGEN0);
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dev_dbg(di->ipu->dev, "%s: inrate: %ld desired: %ld div: 0x%08x\n",
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__func__, parent_rate, rate, div);
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return 0;
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}
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static u8 clk_di_get_parent(struct clk_hw *hw)
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{
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struct ipu_di *di = container_of(hw, struct ipu_di, clk_hw_out);
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u32 val;
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val = ipu_di_read(di, DI_GENERAL);
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return val & DI_GEN_DI_CLK_EXT ? 1 : 0;
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}
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static int clk_di_set_parent(struct clk_hw *hw, u8 index)
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{
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struct ipu_di *di = container_of(hw, struct ipu_di, clk_hw_out);
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u32 val;
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val = ipu_di_read(di, DI_GENERAL);
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if (index)
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val |= DI_GEN_DI_CLK_EXT;
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else
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val &= ~DI_GEN_DI_CLK_EXT;
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ipu_di_write(di, val, DI_GENERAL);
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return 0;
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}
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static struct clk_ops clk_di_ops = {
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.round_rate = clk_di_round_rate,
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.set_rate = clk_di_set_rate,
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.recalc_rate = clk_di_recalc_rate,
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.set_parent = clk_di_set_parent,
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.get_parent = clk_di_get_parent,
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};
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static void ipu_di_data_wave_config(struct ipu_di *di,
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int wave_gen,
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int access_size, int component_size)
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@ -528,42 +398,58 @@ static void ipu_di_sync_config_noninterlaced(struct ipu_di *di,
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ipu_di_sync_config(di, cfg_vga, 0, ARRAY_SIZE(cfg_vga));
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}
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int ipu_di_init_sync_panel(struct ipu_di *di, struct ipu_di_signal_cfg *sig)
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static void ipu_di_config_clock(struct ipu_di *di,
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const struct ipu_di_signal_cfg *sig)
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{
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u32 reg;
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u32 di_gen, vsync_cnt;
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u32 div;
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u32 h_total, v_total;
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int ret;
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unsigned long round;
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struct clk *parent;
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struct clk *clk;
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unsigned clkgen0;
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uint32_t val;
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dev_dbg(di->ipu->dev, "disp %d: panel size = %d x %d\n",
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di->id, sig->width, sig->height);
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if ((sig->v_sync_width == 0) || (sig->h_sync_width == 0))
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return -EINVAL;
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dev_dbg(di->ipu->dev, "Clocks: IPU %luHz DI %luHz Needed %luHz\n",
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clk_get_rate(di->clk_ipu),
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clk_get_rate(di->clk_di),
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sig->pixelclock);
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/*
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* CLKMODE_EXT means we must use the DI clock: this is needed
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* for things like LVDS which needs to feed the DI and LDB with
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* the same pixel clock.
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*
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* For other interfaces, we can arbitarily select between the DI
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* specific clock and the internal IPU clock. See DI_GENERAL
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* bit 20. We select the IPU clock if it can give us a clock
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* rate within 1% of the requested frequency, otherwise we use
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* the DI clock.
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*/
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round = sig->pixelclock;
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if (sig->clkflags & IPU_DI_CLKMODE_EXT) {
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parent = di->clk_di;
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/*
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* CLKMODE_EXT means we must use the DI clock: this is
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* needed for things like LVDS which needs to feed the
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* DI and LDB with the same pixel clock.
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*/
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clk = di->clk_di;
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if (sig->clkflags & IPU_DI_CLKMODE_SYNC) {
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/*
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* CLKMODE_SYNC means that we want the DI to be
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* clocked at the same rate as the parent clock.
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* This is needed (eg) for LDB which needs to be
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* fed with the same pixel clock. We assume that
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* the LDB clock has already been set correctly.
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*/
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clkgen0 = 1 << 4;
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} else {
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/*
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* We can use the divider. We should really have
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* a flag here indicating whether the bridge can
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* cope with a fractional divider or not. For the
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* time being, let's go for simplicitly and
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* reliability.
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*/
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unsigned long in_rate;
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unsigned div;
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clk_set_rate(clk, sig->pixelclock);
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in_rate = clk_get_rate(clk);
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div = (in_rate + sig->pixelclock / 2) / sig->pixelclock;
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if (div == 0)
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div = 1;
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clkgen0 = div << 4;
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}
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} else {
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/*
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* For other interfaces, we can arbitarily select between
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* the DI specific clock and the internal IPU clock. See
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* DI_GENERAL bit 20. We select the IPU clock if it can
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* give us a clock rate within 1% of the requested frequency,
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* otherwise we use the DI clock.
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*/
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unsigned long rate, clkrate;
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unsigned div, error;
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@ -578,54 +464,80 @@ int ipu_di_init_sync_panel(struct ipu_di *di, struct ipu_di_signal_cfg *sig)
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/* Allow a 1% error */
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if (error < 1010 && error >= 990) {
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parent = di->clk_ipu;
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clk = di->clk_ipu;
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clkgen0 = div << 4;
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} else {
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parent = di->clk_di;
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unsigned long in_rate;
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unsigned div;
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ret = clk_set_rate(parent, sig->pixelclock);
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if (ret)
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dev_err(di->ipu->dev, "Setting of DI clock failed: %d\n", ret);
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clk = di->clk_di;
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/* Use the integer divisor rate - avoid fractional dividers */
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round = rate;
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clk_set_rate(clk, sig->pixelclock);
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in_rate = clk_get_rate(clk);
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div = (in_rate + sig->pixelclock / 2) / sig->pixelclock;
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if (div == 0)
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div = 1;
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clkgen0 = div << 4;
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}
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}
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ret = clk_set_parent(di->clk_di_pixel, parent);
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if (ret) {
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dev_err(di->ipu->dev,
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"setting pixel clock to parent %s failed with %d\n",
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__clk_get_name(parent), ret);
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return ret;
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}
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di->clk_di_pixel = clk;
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/* Set the divider */
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ipu_di_write(di, clkgen0, DI_BS_CLKGEN0);
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/*
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* CLKMODE_SYNC means that we want the DI to be clocked at the
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* same rate as the parent clock. This is needed (eg) for LDB
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* which needs to be fed with the same pixel clock.
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*
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* Note: clk_set_rate(clk, clk_round_rate(clk, rate)) is the
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* same as clk_set_rate(clk, rate);
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* Set the high/low periods. Bits 24:16 give us the falling edge,
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* and bits 8:0 give the rising edge. LSB is fraction, and is
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* based on the divider above. We want a 50% duty cycle, so set
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* the falling edge to be half the divider.
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*/
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if (sig->clkflags & IPU_DI_CLKMODE_SYNC)
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round = clk_get_rate(parent);
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ipu_di_write(di, (clkgen0 >> 4) << 16, DI_BS_CLKGEN1);
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ret = clk_set_rate(di->clk_di_pixel, round);
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/* Finally select the input clock */
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val = ipu_di_read(di, DI_GENERAL) & ~DI_GEN_DI_CLK_EXT;
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if (clk == di->clk_di)
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val |= DI_GEN_DI_CLK_EXT;
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ipu_di_write(di, val, DI_GENERAL);
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dev_dbg(di->ipu->dev, "Want %luHz IPU %luHz DI %luHz using %s, got %luHz\n",
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dev_dbg(di->ipu->dev, "Want %luHz IPU %luHz DI %luHz using %s, %luHz\n",
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sig->pixelclock,
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clk_get_rate(di->clk_ipu),
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clk_get_rate(di->clk_di),
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parent == di->clk_di ? "DI" : "IPU",
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clk_get_rate(di->clk_di_pixel));
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clk == di->clk_di ? "DI" : "IPU",
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clk_get_rate(di->clk_di_pixel) / (clkgen0 >> 4));
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}
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int ipu_di_init_sync_panel(struct ipu_di *di, struct ipu_di_signal_cfg *sig)
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{
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u32 reg;
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u32 di_gen, vsync_cnt;
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u32 div;
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u32 h_total, v_total;
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dev_dbg(di->ipu->dev, "disp %d: panel size = %d x %d\n",
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di->id, sig->width, sig->height);
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if ((sig->v_sync_width == 0) || (sig->h_sync_width == 0))
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return -EINVAL;
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h_total = sig->width + sig->h_sync_width + sig->h_start_width +
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sig->h_end_width;
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v_total = sig->height + sig->v_sync_width + sig->v_start_width +
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sig->v_end_width;
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dev_dbg(di->ipu->dev, "Clocks: IPU %luHz DI %luHz Needed %luHz\n",
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clk_get_rate(di->clk_ipu),
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clk_get_rate(di->clk_di),
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sig->pixelclock);
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mutex_lock(&di_mutex);
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ipu_di_config_clock(di, sig);
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div = ipu_di_read(di, DI_BS_CLKGEN0) & 0xfff;
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div = div / 16; /* Now divider is integer portion */
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@ -709,7 +621,11 @@ EXPORT_SYMBOL_GPL(ipu_di_init_sync_panel);
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int ipu_di_enable(struct ipu_di *di)
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{
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int ret = clk_prepare_enable(di->clk_di_pixel);
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int ret;
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WARN_ON(IS_ERR(di->clk_di_pixel));
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ret = clk_prepare_enable(di->clk_di_pixel);
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if (ret)
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return ret;
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@ -721,6 +637,8 @@ EXPORT_SYMBOL_GPL(ipu_di_enable);
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int ipu_di_disable(struct ipu_di *di)
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{
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WARN_ON(IS_ERR(di->clk_di_pixel));
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ipu_module_disable(di->ipu, di->module);
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clk_disable_unprepare(di->clk_di_pixel);
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@ -776,13 +694,6 @@ int ipu_di_init(struct ipu_soc *ipu, struct device *dev, int id,
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u32 module, struct clk *clk_ipu)
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{
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struct ipu_di *di;
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int ret;
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const char *di_parent[2];
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struct clk_init_data init = {
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.ops = &clk_di_ops,
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.num_parents = 2,
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.flags = 0,
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};
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if (id > 1)
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return -ENODEV;
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@ -804,45 +715,16 @@ int ipu_di_init(struct ipu_soc *ipu, struct device *dev, int id,
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if (!di->base)
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return -ENOMEM;
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di_parent[0] = __clk_get_name(di->clk_ipu);
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di_parent[1] = __clk_get_name(di->clk_di);
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ipu_di_write(di, 0x10, DI_BS_CLKGEN0);
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init.parent_names = (const char **)&di_parent;
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di->clk_name = kasprintf(GFP_KERNEL, "%s_di%d_pixel",
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dev_name(dev), id);
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if (!di->clk_name)
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return -ENOMEM;
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init.name = di->clk_name;
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di->clk_hw_out.init = &init;
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di->clk_di_pixel = clk_register(dev, &di->clk_hw_out);
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if (IS_ERR(di->clk_di_pixel)) {
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ret = PTR_ERR(di->clk_di_pixel);
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goto failed_clk_register;
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}
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dev_dbg(dev, "DI%d base: 0x%08lx remapped to %p\n",
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id, base, di->base);
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di->inuse = false;
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di->ipu = ipu;
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return 0;
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failed_clk_register:
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kfree(di->clk_name);
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return ret;
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}
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void ipu_di_exit(struct ipu_soc *ipu, int id)
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{
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struct ipu_di *di = ipu->di_priv[id];
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clk_unregister(di->clk_di_pixel);
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kfree(di->clk_name);
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}
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