x86/pci-dma: remove the experimental forcesac boot option
Limiting the dma mask to avoid PCI (pre-PCIe) DAC cycles while paying the huge overhead of an IOMMU is rather pointless, and this seriously gets in the way of dma mapping work. Signed-off-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
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@ -1705,7 +1705,6 @@
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nopanic
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merge
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nomerge
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forcesac
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soft
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pt [x86, IA-64]
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nobypass [PPC/POWERNV]
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@ -208,7 +208,7 @@ IOMMU (input/output memory management unit)
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Kernel boot message: "PCI-DMA: Using Calgary IOMMU"
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iommu=[<size>][,noagp][,off][,force][,noforce][,leak[=<nr_of_leak_pages>]
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[,memaper[=<order>]][,merge][,forcesac][,fullflush][,nomerge]
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[,memaper[=<order>]][,merge][,fullflush][,nomerge]
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[,noaperture][,calgary]
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General iommu options:
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@ -235,8 +235,6 @@ IOMMU (input/output memory management unit)
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(experimental).
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nomerge Don't do scatter-gather (SG) merging.
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noaperture Ask the IOMMU not to touch the aperture for AGP.
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forcesac Force single-address cycle (SAC) mode for masks <40bits
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(experimental).
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noagp Don't initialize the AGP driver and use full aperture.
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allowdac Allow double-address cycle (DAC) mode, i.e. DMA >4GB.
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DAC is used with 32-bit PCI to push a 64-bit address in
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@ -20,8 +20,6 @@ static int forbid_dac __read_mostly;
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const struct dma_map_ops *dma_ops = &dma_direct_ops;
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EXPORT_SYMBOL(dma_ops);
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static int iommu_sac_force __read_mostly;
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#ifdef CONFIG_IOMMU_DEBUG
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int panic_on_overflow __read_mostly = 1;
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int force_iommu __read_mostly = 1;
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@ -122,7 +120,7 @@ static __init int iommu_setup(char *p)
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if (!strncmp(p, "nomerge", 7))
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iommu_merge = 0;
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if (!strncmp(p, "forcesac", 8))
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iommu_sac_force = 1;
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pr_warn("forcesac option ignored.\n");
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if (!strncmp(p, "allowdac", 8))
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forbid_dac = 0;
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if (!strncmp(p, "nodac", 5))
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@ -162,23 +160,6 @@ int arch_dma_supported(struct device *dev, u64 mask)
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}
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#endif
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/* Tell the device to use SAC when IOMMU force is on. This
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allows the driver to use cheaper accesses in some cases.
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Problem with this is that if we overflow the IOMMU area and
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return DAC as fallback address the device may not handle it
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correctly.
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As a special case some controllers have a 39bit address
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mode that is as efficient as 32bit (aic79xx). Don't force
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SAC for these. Assume all masks <= 40 bits are of this
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type. Normally this doesn't make any difference, but gives
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more gentle handling of IOMMU overflow. */
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if (iommu_sac_force && (mask >= DMA_BIT_MASK(40))) {
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dev_info(dev, "Force SAC with mask %Lx\n", mask);
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return 0;
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}
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return 1;
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}
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EXPORT_SYMBOL(arch_dma_supported);
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@ -1289,9 +1289,8 @@ static int efx_init_io(struct efx_nic *efx)
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pci_set_master(pci_dev);
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/* Set the PCI DMA mask. Try all possibilities from our
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* genuine mask down to 32 bits, because some architectures
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* (e.g. x86_64 with iommu_sac_force set) will allow 40 bit
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/* Set the PCI DMA mask. Try all possibilities from our genuine mask
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* down to 32 bits, because some architectures will allow 40 bit
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* masks event though they reject 46 bit masks.
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*/
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while (dma_mask > 0x7fffffffUL) {
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@ -1242,9 +1242,8 @@ static int ef4_init_io(struct ef4_nic *efx)
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pci_set_master(pci_dev);
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/* Set the PCI DMA mask. Try all possibilities from our
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* genuine mask down to 32 bits, because some architectures
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* (e.g. x86_64 with iommu_sac_force set) will allow 40 bit
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/* Set the PCI DMA mask. Try all possibilities from our genuine mask
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* down to 32 bits, because some architectures will allow 40 bit
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* masks event though they reject 46 bit masks.
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*/
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while (dma_mask > 0x7fffffffUL) {
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