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clk: samsung: exynos5433: Add clocks for CMU_MIF domain

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This patch adds the mux/divider/gate clocks of CMU_MIF domain which includes
the clocks for DMC(DRAM memory controller) and CCI(Cache Coherent Interconnect).
The CMU_MIF domain provides the source clocks for CMU_DISP/CMU_BUS2.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Inki Dae <inki.dae@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
This commit is contained in:
Chanwoo Choi
2015-02-02 23:24:01 +09:00
committed by Sylwester Nawrocki
parent a29308dad5
commit 06d2f9dfa6
2 changed files with 788 additions and 1 deletions
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190
include/dt-bindings/clock/exynos5433.h
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@@ -149,8 +149,196 @@
#define CLK_FOUT_MEM1_PLL 2
#define CLK_FOUT_BUS_PLL 3
#define CLK_FOUT_MFC_PLL 4
#define CLK_DOUT_MFC_PLL 5
#define CLK_DOUT_BUS_PLL 6
#define CLK_DOUT_MEM1_PLL 7
#define CLK_DOUT_MEM0_PLL 8
#define MIF_NR_CLK 5
#define CLK_MOUT_MFC_PLL_DIV2 10
#define CLK_MOUT_BUS_PLL_DIV2 11
#define CLK_MOUT_MEM1_PLL_DIV2 12
#define CLK_MOUT_MEM0_PLL_DIV2 13
#define CLK_MOUT_MFC_PLL 14
#define CLK_MOUT_BUS_PLL 15
#define CLK_MOUT_MEM1_PLL 16
#define CLK_MOUT_MEM0_PLL 17
#define CLK_MOUT_CLK2X_PHY_C 18
#define CLK_MOUT_CLK2X_PHY_B 19
#define CLK_MOUT_CLK2X_PHY_A 20
#define CLK_MOUT_CLKM_PHY_C 21
#define CLK_MOUT_CLKM_PHY_B 22
#define CLK_MOUT_CLKM_PHY_A 23
#define CLK_MOUT_ACLK_MIFNM_200 24
#define CLK_MOUT_ACLK_MIFNM_400 25
#define CLK_MOUT_ACLK_DISP_333_B 26
#define CLK_MOUT_ACLK_DISP_333_A 27
#define CLK_MOUT_SCLK_DECON_VCLK_C 28
#define CLK_MOUT_SCLK_DECON_VCLK_B 29
#define CLK_MOUT_SCLK_DECON_VCLK_A 30
#define CLK_MOUT_SCLK_DECON_ECLK_C 31
#define CLK_MOUT_SCLK_DECON_ECLK_B 32
#define CLK_MOUT_SCLK_DECON_ECLK_A 33
#define CLK_MOUT_SCLK_DECON_TV_ECLK_C 34
#define CLK_MOUT_SCLK_DECON_TV_ECLK_B 35
#define CLK_MOUT_SCLK_DECON_TV_ECLK_A 36
#define CLK_MOUT_SCLK_DSD_C 37
#define CLK_MOUT_SCLK_DSD_B 38
#define CLK_MOUT_SCLK_DSD_A 39
#define CLK_MOUT_SCLK_DSIM0_C 40
#define CLK_MOUT_SCLK_DSIM0_B 41
#define CLK_MOUT_SCLK_DSIM0_A 42
#define CLK_MOUT_SCLK_DECON_TV_VCLK_C 46
#define CLK_MOUT_SCLK_DECON_TV_VCLK_B 47
#define CLK_MOUT_SCLK_DECON_TV_VCLK_A 48
#define CLK_MOUT_SCLK_DSIM1_C 49
#define CLK_MOUT_SCLK_DSIM1_B 50
#define CLK_MOUT_SCLK_DSIM1_A 51
#define CLK_DIV_SCLK_HPM_MIF 55
#define CLK_DIV_ACLK_DREX1 56
#define CLK_DIV_ACLK_DREX0 57
#define CLK_DIV_CLK2XPHY 58
#define CLK_DIV_ACLK_MIF_266 59
#define CLK_DIV_ACLK_MIFND_133 60
#define CLK_DIV_ACLK_MIF_133 61
#define CLK_DIV_ACLK_MIFNM_200 62
#define CLK_DIV_ACLK_MIF_200 63
#define CLK_DIV_ACLK_MIF_400 64
#define CLK_DIV_ACLK_BUS2_400 65
#define CLK_DIV_ACLK_DISP_333 66
#define CLK_DIV_ACLK_CPIF_200 67
#define CLK_DIV_SCLK_DSIM1 68
#define CLK_DIV_SCLK_DECON_TV_VCLK 69
#define CLK_DIV_SCLK_DSIM0 70
#define CLK_DIV_SCLK_DSD 71
#define CLK_DIV_SCLK_DECON_TV_ECLK 72
#define CLK_DIV_SCLK_DECON_VCLK 73
#define CLK_DIV_SCLK_DECON_ECLK 74
#define CLK_DIV_MIF_PRE 75
#define CLK_CLK2X_PHY1 80
#define CLK_CLK2X_PHY0 81
#define CLK_CLKM_PHY1 82
#define CLK_CLKM_PHY0 83
#define CLK_RCLK_DREX1 84
#define CLK_RCLK_DREX0 85
#define CLK_ACLK_DREX1_TZ 86
#define CLK_ACLK_DREX0_TZ 87
#define CLK_ACLK_DREX1_PEREV 88
#define CLK_ACLK_DREX0_PEREV 89
#define CLK_ACLK_DREX1_MEMIF 90
#define CLK_ACLK_DREX0_MEMIF 91
#define CLK_ACLK_DREX1_SCH 92
#define CLK_ACLK_DREX0_SCH 93
#define CLK_ACLK_DREX1_BUSIF 94
#define CLK_ACLK_DREX0_BUSIF 95
#define CLK_ACLK_DREX1_BUSIF_RD 96
#define CLK_ACLK_DREX0_BUSIF_RD 97
#define CLK_ACLK_DREX1 98
#define CLK_ACLK_DREX0 99
#define CLK_ACLK_ASYNCAXIM_ATLAS_CCIX 100
#define CLK_ACLK_ASYNCAXIS_ATLAS_MIF 101
#define CLK_ACLK_ASYNCAXIM_ATLAS_MIF 102
#define CLK_ACLK_ASYNCAXIS_MIF_IMEM 103
#define CLK_ACLK_ASYNCAXIS_NOC_P_CCI 104
#define CLK_ACLK_ASYNCAXIM_NOC_P_CCI 105
#define CLK_ACLK_ASYNCAXIS_CP1 106
#define CLK_ACLK_ASYNCAXIM_CP1 107
#define CLK_ACLK_ASYNCAXIS_CP0 108
#define CLK_ACLK_ASYNCAXIM_CP0 109
#define CLK_ACLK_ASYNCAXIS_DREX1_3 110
#define CLK_ACLK_ASYNCAXIM_DREX1_3 111
#define CLK_ACLK_ASYNCAXIS_DREX1_1 112
#define CLK_ACLK_ASYNCAXIM_DREX1_1 113
#define CLK_ACLK_ASYNCAXIS_DREX1_0 114
#define CLK_ACLK_ASYNCAXIM_DREX1_0 115
#define CLK_ACLK_ASYNCAXIS_DREX0_3 116
#define CLK_ACLK_ASYNCAXIM_DREX0_3 117
#define CLK_ACLK_ASYNCAXIS_DREX0_1 118
#define CLK_ACLK_ASYNCAXIM_DREX0_1 119
#define CLK_ACLK_ASYNCAXIS_DREX0_0 120
#define CLK_ACLK_ASYNCAXIM_DREX0_0 121
#define CLK_ACLK_AHB2APB_MIF2P 122
#define CLK_ACLK_AHB2APB_MIF1P 123
#define CLK_ACLK_AHB2APB_MIF0P 124
#define CLK_ACLK_IXIU_CCI 125
#define CLK_ACLK_XIU_MIFSFRX 126
#define CLK_ACLK_MIFNP_133 127
#define CLK_ACLK_MIFNM_200 128
#define CLK_ACLK_MIFND_133 129
#define CLK_ACLK_MIFND_400 130
#define CLK_ACLK_CCI 131
#define CLK_ACLK_MIFND_266 132
#define CLK_ACLK_PPMU_DREX1S3 133
#define CLK_ACLK_PPMU_DREX1S1 134
#define CLK_ACLK_PPMU_DREX1S0 135
#define CLK_ACLK_PPMU_DREX0S3 136
#define CLK_ACLK_PPMU_DREX0S1 137
#define CLK_ACLK_PPMU_DREX0S0 138
#define CLK_ACLK_BTS_APOLLO 139
#define CLK_ACLK_BTS_ATLAS 140
#define CLK_ACLK_ACE_SEL_APOLL 141
#define CLK_ACLK_ACE_SEL_ATLAS 142
#define CLK_ACLK_AXIDS_CCI_MIFSFRX 143
#define CLK_ACLK_AXIUS_ATLAS_CCI 144
#define CLK_ACLK_AXISYNCDNS_CCI 145
#define CLK_ACLK_AXISYNCDN_CCI 146
#define CLK_ACLK_AXISYNCDN_NOC_D 147
#define CLK_ACLK_ASYNCACEM_APOLLO_CCI 148
#define CLK_ACLK_ASYNCACEM_ATLAS_CCI 149
#define CLK_ACLK_ASYNCAPBS_MIF_CSSYS 150
#define CLK_ACLK_BUS2_400 151
#define CLK_ACLK_DISP_333 152
#define CLK_ACLK_CPIF_200 153
#define CLK_PCLK_PPMU_DREX1S3 154
#define CLK_PCLK_PPMU_DREX1S1 155
#define CLK_PCLK_PPMU_DREX1S0 156
#define CLK_PCLK_PPMU_DREX0S3 157
#define CLK_PCLK_PPMU_DREX0S1 158
#define CLK_PCLK_PPMU_DREX0S0 159
#define CLK_PCLK_BTS_APOLLO 160
#define CLK_PCLK_BTS_ATLAS 161
#define CLK_PCLK_ASYNCAXI_NOC_P_CCI 162
#define CLK_PCLK_ASYNCAXI_CP1 163
#define CLK_PCLK_ASYNCAXI_CP0 164
#define CLK_PCLK_ASYNCAXI_DREX1_3 165
#define CLK_PCLK_ASYNCAXI_DREX1_1 166
#define CLK_PCLK_ASYNCAXI_DREX1_0 167
#define CLK_PCLK_ASYNCAXI_DREX0_3 168
#define CLK_PCLK_ASYNCAXI_DREX0_1 169
#define CLK_PCLK_ASYNCAXI_DREX0_0 170
#define CLK_PCLK_MIFSRVND_133 171
#define CLK_PCLK_PMU_MIF 172
#define CLK_PCLK_SYSREG_MIF 173
#define CLK_PCLK_GPIO_ALIVE 174
#define CLK_PCLK_ABB 175
#define CLK_PCLK_PMU_APBIF 176
#define CLK_PCLK_DDR_PHY1 177
#define CLK_PCLK_DREX1 178
#define CLK_PCLK_DDR_PHY0 179
#define CLK_PCLK_DREX0 180
#define CLK_PCLK_DREX0_TZ 181
#define CLK_PCLK_DREX1_TZ 182
#define CLK_PCLK_MONOTONIC_CNT 183
#define CLK_PCLK_RTC 184
#define CLK_SCLK_DSIM1_DISP 185
#define CLK_SCLK_DECON_TV_VCLK_DISP 186
#define CLK_SCLK_FREQ_DET_BUS_PLL 187
#define CLK_SCLK_FREQ_DET_MFC_PLL 188
#define CLK_SCLK_FREQ_DET_MEM0_PLL 189
#define CLK_SCLK_FREQ_DET_MEM1_PLL 190
#define CLK_SCLK_DSIM0_DISP 191
#define CLK_SCLK_DSD_DISP 192
#define CLK_SCLK_DECON_TV_ECLK_DISP 193
#define CLK_SCLK_DECON_VCLK_DISP 194
#define CLK_SCLK_DECON_ECLK_DISP 195
#define CLK_SCLK_HPM_MIF 196
#define CLK_SCLK_MFC_PLL 197
#define CLK_SCLK_BUS_PLL 198
#define CLK_SCLK_BUS_PLL_APOLLO 199
#define CLK_SCLK_BUS_PLL_ATLAS 200
#define MIF_NR_CLK 201
/* CMU_PERIC */
#define CLK_PCLK_SPI2 1