drm/i915/hsw: Split out the SPLL parameter calculation
For consistency with the WRPLL/LCPLL parameter calculation functions, split out the SPLL specific logic to its own function. Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200226203455.23032-10-imre.deak@intel.com
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@ -956,6 +956,23 @@ hsw_ddi_lcpll_get_dpll(struct intel_crtc_state *crtc_state)
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return pll;
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}
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static struct intel_shared_dpll *
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hsw_ddi_spll_get_dpll(struct intel_atomic_state *state,
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struct intel_crtc *crtc)
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{
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struct intel_crtc_state *crtc_state =
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intel_atomic_get_new_crtc_state(state, crtc);
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if (WARN_ON(crtc_state->port_clock / 2 != 135000))
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return NULL;
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crtc_state->dpll_hw_state.spll = SPLL_PLL_ENABLE | SPLL_FREQ_1350MHz |
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SPLL_REF_MUXED_SSC;
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return intel_find_shared_dpll(state, crtc, &crtc_state->dpll_hw_state,
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BIT(DPLL_ID_SPLL));
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}
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static bool hsw_get_dpll(struct intel_atomic_state *state,
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struct intel_crtc *crtc,
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struct intel_encoder *encoder)
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@ -967,23 +984,14 @@ static bool hsw_get_dpll(struct intel_atomic_state *state,
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memset(&crtc_state->dpll_hw_state, 0,
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sizeof(crtc_state->dpll_hw_state));
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if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
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if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
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pll = hsw_ddi_wrpll_get_dpll(state, crtc);
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} else if (intel_crtc_has_dp_encoder(crtc_state)) {
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else if (intel_crtc_has_dp_encoder(crtc_state))
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pll = hsw_ddi_lcpll_get_dpll(crtc_state);
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} else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
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if (WARN_ON(crtc_state->port_clock / 2 != 135000))
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return false;
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crtc_state->dpll_hw_state.spll =
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SPLL_PLL_ENABLE | SPLL_FREQ_1350MHz | SPLL_REF_MUXED_SSC;
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pll = intel_find_shared_dpll(state, crtc,
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&crtc_state->dpll_hw_state,
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BIT(DPLL_ID_SPLL));
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} else {
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else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
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pll = hsw_ddi_spll_get_dpll(state, crtc);
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else
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return false;
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}
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if (!pll)
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return false;
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