forked from Minki/linux
x86/PCI: host mmconfig detect clean up
Fix mmconfig detection to not assume a single mmconfig space in the northbridge, paving the way for AMD fam10h + mcp55 CPUs. On those, the MSR has some range, but the mcp55 pci config will have another one. Also helps the mcp55 + io55 case, where every one will have one range. If it is mcp55, exclude the range that is used by CPU MSR, in other words , if the CPU claims busses 0-255, the range in mcp55 is dropped, because CPU HW will not route those ranges to mcp55 mmconfig to handle it. Signed-off-by: Yinghai Lu <yinghai.lu@kernel.org> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
This commit is contained in:
Yinghai Lu
Jesse Barnes
parent
fafad5bf06
commit
068258bc15
@ -14,6 +14,7 @@
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#include <linux/init.h>
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#include <linux/acpi.h>
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#include <linux/bitmap.h>
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#include <linux/sort.h>
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#include <asm/e820.h>
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#include <asm/pci_x86.h>
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@ -24,24 +25,49 @@
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/* Indicate if the mmcfg resources have been placed into the resource table. */
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static int __initdata pci_mmcfg_resources_inserted;
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static __init int extend_mmcfg(int num)
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{
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struct acpi_mcfg_allocation *new;
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int new_num = pci_mmcfg_config_num + num;
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new = kzalloc(sizeof(pci_mmcfg_config[0]) * new_num, GFP_KERNEL);
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if (!new)
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return -1;
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if (pci_mmcfg_config) {
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memcpy(new, pci_mmcfg_config,
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sizeof(pci_mmcfg_config[0]) * new_num);
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kfree(pci_mmcfg_config);
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}
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pci_mmcfg_config = new;
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return 0;
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}
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static __init void fill_one_mmcfg(u64 addr, int segment, int start, int end)
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{
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int i = pci_mmcfg_config_num;
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pci_mmcfg_config_num++;
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pci_mmcfg_config[i].address = addr;
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pci_mmcfg_config[i].pci_segment = segment;
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pci_mmcfg_config[i].start_bus_number = start;
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pci_mmcfg_config[i].end_bus_number = end;
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}
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static const char __init *pci_mmcfg_e7520(void)
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{
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u32 win;
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raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0xce, 2, &win);
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win = win & 0xf000;
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if(win == 0x0000 || win == 0xf000)
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pci_mmcfg_config_num = 0;
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else {
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pci_mmcfg_config_num = 1;
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pci_mmcfg_config = kzalloc(sizeof(pci_mmcfg_config[0]), GFP_KERNEL);
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if (!pci_mmcfg_config)
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return NULL;
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pci_mmcfg_config[0].address = win << 16;
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pci_mmcfg_config[0].pci_segment = 0;
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pci_mmcfg_config[0].start_bus_number = 0;
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pci_mmcfg_config[0].end_bus_number = 255;
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}
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if (win == 0x0000 || win == 0xf000)
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return NULL;
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if (extend_mmcfg(1) == -1)
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return NULL;
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fill_one_mmcfg(win << 16, 0, 0, 255);
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return "Intel Corporation E7520 Memory Controller Hub";
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}
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@ -50,13 +76,11 @@ static const char __init *pci_mmcfg_intel_945(void)
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{
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u32 pciexbar, mask = 0, len = 0;
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pci_mmcfg_config_num = 1;
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raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0x48, 4, &pciexbar);
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/* Enable bit */
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if (!(pciexbar & 1))
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pci_mmcfg_config_num = 0;
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return NULL;
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/* Size bits */
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switch ((pciexbar >> 1) & 3) {
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@ -73,28 +97,23 @@ static const char __init *pci_mmcfg_intel_945(void)
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len = 0x04000000U;
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break;
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default:
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pci_mmcfg_config_num = 0;
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return NULL;
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}
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/* Errata #2, things break when not aligned on a 256Mb boundary */
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/* Can only happen in 64M/128M mode */
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if ((pciexbar & mask) & 0x0fffffffU)
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pci_mmcfg_config_num = 0;
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return NULL;
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/* Don't hit the APIC registers and their friends */
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if ((pciexbar & mask) >= 0xf0000000U)
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pci_mmcfg_config_num = 0;
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return NULL;
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if (pci_mmcfg_config_num) {
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pci_mmcfg_config = kzalloc(sizeof(pci_mmcfg_config[0]), GFP_KERNEL);
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if (!pci_mmcfg_config)
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return NULL;
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pci_mmcfg_config[0].address = pciexbar & mask;
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pci_mmcfg_config[0].pci_segment = 0;
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pci_mmcfg_config[0].start_bus_number = 0;
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pci_mmcfg_config[0].end_bus_number = (len >> 20) - 1;
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}
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if (extend_mmcfg(1) == -1)
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return NULL;
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fill_one_mmcfg(pciexbar & mask, 0, 0, (len >> 20) - 1);
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return "Intel Corporation 945G/GZ/P/PL Express Memory Controller Hub";
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}
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@ -138,18 +157,11 @@ static const char __init *pci_mmcfg_amd_fam10h(void)
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busnbits = 8;
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}
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pci_mmcfg_config_num = (1 << segnbits);
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pci_mmcfg_config = kzalloc(sizeof(pci_mmcfg_config[0]) *
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pci_mmcfg_config_num, GFP_KERNEL);
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if (!pci_mmcfg_config)
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if (extend_mmcfg(1 << segnbits) == -1)
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return NULL;
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for (i = 0; i < (1 << segnbits); i++) {
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pci_mmcfg_config[i].address = base + (1<<28) * i;
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pci_mmcfg_config[i].pci_segment = i;
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pci_mmcfg_config[i].start_bus_number = 0;
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pci_mmcfg_config[i].end_bus_number = (1 << busnbits) - 1;
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}
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for (i = 0; i < (1 << segnbits); i++)
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fill_one_mmcfg(base + (1<<28) * i, i, 0, (1 << busnbits) - 1);
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return "AMD Family 10h NB";
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}
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@ -237,6 +249,48 @@ static struct pci_mmcfg_hostbridge_probe pci_mmcfg_probes[] __initdata = {
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0x0369, pci_mmcfg_nvidia_mcp55 },
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};
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static int __init cmp_mmcfg(const void *x1, const void *x2)
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{
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const typeof(pci_mmcfg_config[0]) *m1 = x1;
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const typeof(pci_mmcfg_config[0]) *m2 = x2;
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int start1, start2;
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start1 = m1->start_bus_number;
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start2 = m2->start_bus_number;
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return start1 - start2;
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}
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static void __init pci_mmcfg_check_end_bus_number(void)
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{
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int i;
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typeof(pci_mmcfg_config[0]) *cfg, *cfgx;
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/* sort them at first */
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sort(pci_mmcfg_config, pci_mmcfg_config_num,
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sizeof(pci_mmcfg_config[0]), cmp_mmcfg, NULL);
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/* last one*/
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if (pci_mmcfg_config_num > 0) {
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i = pci_mmcfg_config_num - 1;
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cfg = &pci_mmcfg_config[i];
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if (cfg->end_bus_number < cfg->start_bus_number)
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cfg->end_bus_number = 255;
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}
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/* don't overlap please */
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for (i = 0; i < pci_mmcfg_config_num - 1; i++) {
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cfg = &pci_mmcfg_config[i];
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cfgx = &pci_mmcfg_config[i+1];
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if (cfg->end_bus_number < cfg->start_bus_number)
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cfg->end_bus_number = 255;
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if (cfg->end_bus_number >= cfgx->start_bus_number)
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cfg->end_bus_number = cfgx->start_bus_number - 1;
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}
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}
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static int __init pci_mmcfg_check_hostbridge(void)
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{
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u32 l;
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@ -250,31 +304,33 @@ static int __init pci_mmcfg_check_hostbridge(void)
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pci_mmcfg_config_num = 0;
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pci_mmcfg_config = NULL;
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name = NULL;
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for (i = 0; !name && i < ARRAY_SIZE(pci_mmcfg_probes); i++) {
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for (i = 0; i < ARRAY_SIZE(pci_mmcfg_probes); i++) {
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bus = pci_mmcfg_probes[i].bus;
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devfn = pci_mmcfg_probes[i].devfn;
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raw_pci_ops->read(0, bus, devfn, 0, 4, &l);
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vendor = l & 0xffff;
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device = (l >> 16) & 0xffff;
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name = NULL;
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if (pci_mmcfg_probes[i].vendor == vendor &&
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pci_mmcfg_probes[i].device == device)
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name = pci_mmcfg_probes[i].probe();
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if (name)
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printk(KERN_INFO "PCI: Found %s with MMCONFIG support.\n",
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name);
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}
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if (name) {
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printk(KERN_INFO "PCI: Found %s %s MMCONFIG support.\n",
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name, pci_mmcfg_config_num ? "with" : "without");
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}
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/* some end_bus_number is crazy, fix it */
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pci_mmcfg_check_end_bus_number();
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return name != NULL;
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return pci_mmcfg_config_num != 0;
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}
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static void __init pci_mmcfg_insert_resources(void)
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{
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#define PCI_MMCFG_RESOURCE_NAME_LEN 19
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#define PCI_MMCFG_RESOURCE_NAME_LEN 24
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int i;
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struct resource *res;
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char *names;
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@ -292,9 +348,10 @@ static void __init pci_mmcfg_insert_resources(void)
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struct acpi_mcfg_allocation *cfg = &pci_mmcfg_config[i];
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num_buses = cfg->end_bus_number - cfg->start_bus_number + 1;
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res->name = names;
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snprintf(names, PCI_MMCFG_RESOURCE_NAME_LEN, "PCI MMCONFIG %u",
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cfg->pci_segment);
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res->start = cfg->address;
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snprintf(names, PCI_MMCFG_RESOURCE_NAME_LEN,
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"PCI MMCONFIG %u [%02x-%02x]", cfg->pci_segment,
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cfg->start_bus_number, cfg->end_bus_number);
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res->start = cfg->address + (cfg->start_bus_number << 20);
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res->end = res->start + (num_buses << 20) - 1;
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res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
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insert_resource(&iomem_resource, res);
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@ -418,8 +475,6 @@ static void __init pci_mmcfg_reject_broken(int early)
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(pci_mmcfg_config[0].address == 0))
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return;
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cfg = &pci_mmcfg_config[0];
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for (i = 0; i < pci_mmcfg_config_num; i++) {
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int valid = 0;
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u64 addr, size;
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@ -487,10 +542,10 @@ static void __init __pci_mmcfg_init(int early)
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known_bridge = 1;
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}
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if (!known_bridge) {
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if (!known_bridge)
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acpi_table_parse(ACPI_SIG_MCFG, acpi_parse_mcfg);
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pci_mmcfg_reject_broken(early);
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}
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pci_mmcfg_reject_broken(early);
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if ((pci_mmcfg_config_num == 0) ||
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(pci_mmcfg_config == NULL) ||
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@ -112,13 +112,18 @@ static struct pci_raw_ops pci_mmcfg = {
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static void __iomem * __init mcfg_ioremap(struct acpi_mcfg_allocation *cfg)
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{
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void __iomem *addr;
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u32 size;
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u64 start, size;
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size = (cfg->end_bus_number + 1) << 20;
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addr = ioremap_nocache(cfg->address, size);
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start = cfg->start_bus_number;
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start <<= 20;
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start += cfg->address;
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size = cfg->end_bus_number + 1 - cfg->start_bus_number;
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size <<= 20;
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addr = ioremap_nocache(start, size);
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if (addr) {
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printk(KERN_INFO "PCI: Using MMCONFIG at %Lx - %Lx\n",
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cfg->address, cfg->address + size - 1);
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start, start + size - 1);
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addr -= cfg->start_bus_number << 20;
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}
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return addr;
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}
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@ -157,7 +162,7 @@ void __init pci_mmcfg_arch_free(void)
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for (i = 0; i < pci_mmcfg_config_num; ++i) {
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if (pci_mmcfg_virt[i].virt) {
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iounmap(pci_mmcfg_virt[i].virt);
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iounmap(pci_mmcfg_virt[i].virt + (pci_mmcfg_virt[i].cfg->start_bus_number << 20));
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pci_mmcfg_virt[i].virt = NULL;
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pci_mmcfg_virt[i].cfg = NULL;
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}
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