forked from Minki/linux
iwlwifi: pcie: cleanup old transport code from gen2
Cleanup code that is irrelevant for a000 devices. Signed-off-by: Sara Sharon <sara.sharon@intel.com> Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
This commit is contained in:
parent
cfbeb59824
commit
066fd29a2f
@ -766,10 +766,6 @@ void iwl_pcie_synchronize_irqs(struct iwl_trans *trans);
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bool iwl_trans_check_hw_rf_kill(struct iwl_trans *trans);
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void iwl_pcie_txq_free_tfd(struct iwl_trans *trans, struct iwl_txq *txq);
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int iwl_queue_space(const struct iwl_txq *q);
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int iwl_fill_data_tbs_amsdu(struct iwl_trans *trans, struct sk_buff *skb,
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struct iwl_txq *txq, u8 hdr_len,
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struct iwl_cmd_meta *out_meta,
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struct iwl_device_cmd *dev_cmd, u16 tb1_len);
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/* transport gen 2 exported functions */
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int iwl_trans_pcie_gen2_start_fw(struct iwl_trans *trans,
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@ -98,88 +98,23 @@ static void iwl_pcie_gen2_update_byte_tbl(struct iwl_trans *trans,
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static void iwl_pcie_gen2_txq_inc_wr_ptr(struct iwl_trans *trans,
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struct iwl_txq *txq)
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{
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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u32 reg = 0;
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int txq_id = txq->id;
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lockdep_assert_held(&txq->lock);
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/*
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* explicitly wake up the NIC if:
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* 1. shadow registers aren't enabled
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* 2. NIC is woken up for CMD regardless of shadow outside this function
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* 3. there is a chance that the NIC is asleep
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*/
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if (!trans->cfg->base_params->shadow_reg_enable &&
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txq_id != trans_pcie->cmd_queue &&
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test_bit(STATUS_TPOWER_PMI, &trans->status)) {
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/*
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* wake up nic if it's powered down ...
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* uCode will wake up, and interrupt us again, so next
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* time we'll skip this part.
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*/
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reg = iwl_read32(trans, CSR_UCODE_DRV_GP1);
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if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
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IWL_DEBUG_INFO(trans,
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"Tx queue %d requesting wakeup, GP1 = 0x%x\n",
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txq_id, reg);
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iwl_set_bit(trans, CSR_GP_CNTRL,
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CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
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txq->need_update = true;
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return;
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}
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}
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IWL_DEBUG_TX(trans, "Q:%d WR: 0x%x\n", txq->id, txq->write_ptr);
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/*
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* if not in power-save mode, uCode will never sleep when we're
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* trying to tx (during RFKILL, we're not trying to tx).
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*/
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IWL_DEBUG_TX(trans, "Q:%d WR: 0x%x\n", txq_id, txq->write_ptr);
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if (!txq->block)
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iwl_write32(trans, HBUS_TARG_WRPTR,
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txq->write_ptr | (txq_id << 8));
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txq->write_ptr | (txq->id << 8));
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}
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static inline u8 iwl_pcie_gen2_get_num_tbs(struct iwl_trans *trans, void *_tfd)
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static u8 iwl_pcie_gen2_get_num_tbs(struct iwl_trans *trans,
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struct iwl_tfh_tfd *tfd)
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{
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if (trans->cfg->use_tfh) {
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struct iwl_tfh_tfd *tfd = _tfd;
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return le16_to_cpu(tfd->num_tbs) & 0x1f;
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} else {
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struct iwl_tfd *tfd = _tfd;
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return tfd->num_tbs & 0x1f;
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}
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}
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static inline dma_addr_t iwl_pcie_gen2_tb_get_addr(struct iwl_trans *trans,
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void *_tfd, u8 idx)
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{
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if (trans->cfg->use_tfh) {
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struct iwl_tfh_tfd *tfd = _tfd;
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struct iwl_tfh_tb *tb = &tfd->tbs[idx];
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return (dma_addr_t)(le64_to_cpu(tb->addr));
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} else {
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struct iwl_tfd *tfd = _tfd;
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struct iwl_tfd_tb *tb = &tfd->tbs[idx];
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dma_addr_t addr = get_unaligned_le32(&tb->lo);
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dma_addr_t hi_len;
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if (sizeof(dma_addr_t) <= sizeof(u32))
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return addr;
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hi_len = le16_to_cpu(tb->hi_n_len) & 0xF;
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/*
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* shift by 16 twice to avoid warnings on 32-bit
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* (where this code never runs anyway due to the
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* if statement above)
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*/
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return addr | ((hi_len << 16) << 16);
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}
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return le16_to_cpu(tfd->num_tbs) & 0x1f;
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}
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static void iwl_pcie_gen2_tfd_unmap(struct iwl_trans *trans,
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@ -188,45 +123,31 @@ static void iwl_pcie_gen2_tfd_unmap(struct iwl_trans *trans,
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{
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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int i, num_tbs;
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void *tfd = iwl_pcie_get_tfd(trans_pcie, txq, index);
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struct iwl_tfh_tfd *tfd = iwl_pcie_get_tfd(trans_pcie, txq, index);
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/* Sanity check on number of chunks */
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num_tbs = iwl_pcie_gen2_get_num_tbs(trans, tfd);
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if (num_tbs >= trans_pcie->max_tbs) {
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IWL_ERR(trans, "Too many chunks: %i\n", num_tbs);
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/* @todo issue fatal error, it is quite serious situation */
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return;
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}
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/* first TB is never freed - it's the bidirectional DMA data */
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for (i = 1; i < num_tbs; i++) {
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if (meta->tbs & BIT(i))
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dma_unmap_page(trans->dev,
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iwl_pcie_gen2_tb_get_addr(trans, tfd,
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i),
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iwl_pcie_gen2_tb_get_addr(trans, tfd,
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i),
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le64_to_cpu(tfd->tbs[i].addr),
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le16_to_cpu(tfd->tbs[i].tb_len),
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DMA_TO_DEVICE);
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else
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dma_unmap_single(trans->dev,
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iwl_pcie_gen2_tb_get_addr(trans, tfd,
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i),
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iwl_pcie_gen2_tb_get_addr(trans, tfd,
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i),
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le64_to_cpu(tfd->tbs[i].addr),
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le16_to_cpu(tfd->tbs[i].tb_len),
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DMA_TO_DEVICE);
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}
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if (trans->cfg->use_tfh) {
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struct iwl_tfh_tfd *tfd_fh = (void *)tfd;
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tfd_fh->num_tbs = 0;
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} else {
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struct iwl_tfd *tfd_fh = (void *)tfd;
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tfd_fh->num_tbs = 0;
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}
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tfd->num_tbs = 0;
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}
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static void iwl_pcie_gen2_free_tfd(struct iwl_trans *trans, struct iwl_txq *txq)
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@ -264,27 +185,13 @@ static void iwl_pcie_gen2_free_tfd(struct iwl_trans *trans, struct iwl_txq *txq)
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static inline void iwl_pcie_gen2_set_tb(struct iwl_trans *trans, void *tfd,
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u8 idx, dma_addr_t addr, u16 len)
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{
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if (trans->cfg->use_tfh) {
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struct iwl_tfh_tfd *tfd_fh = (void *)tfd;
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struct iwl_tfh_tb *tb = &tfd_fh->tbs[idx];
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struct iwl_tfh_tfd *tfd_fh = (void *)tfd;
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struct iwl_tfh_tb *tb = &tfd_fh->tbs[idx];
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put_unaligned_le64(addr, &tb->addr);
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tb->tb_len = cpu_to_le16(len);
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put_unaligned_le64(addr, &tb->addr);
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tb->tb_len = cpu_to_le16(len);
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tfd_fh->num_tbs = cpu_to_le16(idx + 1);
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} else {
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struct iwl_tfd *tfd_fh = (void *)tfd;
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struct iwl_tfd_tb *tb = &tfd_fh->tbs[idx];
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u16 hi_n_len = len << 4;
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put_unaligned_le32(addr, &tb->lo);
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hi_n_len |= iwl_get_dma_hi_addr(addr);
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tb->hi_n_len = cpu_to_le16(hi_n_len);
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tfd_fh->num_tbs = idx + 1;
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}
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tfd_fh->num_tbs = cpu_to_le16(idx + 1);
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}
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int iwl_pcie_gen2_build_tfd(struct iwl_trans *trans, struct iwl_txq *txq,
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@ -391,11 +298,9 @@ int iwl_trans_pcie_gen2_tx(struct iwl_trans *trans, struct sk_buff *skb,
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void *tb1_addr;
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void *tfd;
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u16 len, tb1_len;
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bool wait_write_ptr;
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__le16 fc;
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u8 hdr_len;
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u16 wifi_seq;
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bool amsdu;
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txq = &trans_pcie->txq[txq_id];
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@ -403,21 +308,6 @@ int iwl_trans_pcie_gen2_tx(struct iwl_trans *trans, struct sk_buff *skb,
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"TX on unused queue %d\n", txq_id))
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return -EINVAL;
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if (unlikely(trans_pcie->sw_csum_tx &&
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skb->ip_summed == CHECKSUM_PARTIAL)) {
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int offs = skb_checksum_start_offset(skb);
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int csum_offs = offs + skb->csum_offset;
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__wsum csum;
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if (skb_ensure_writable(skb, csum_offs + sizeof(__sum16)))
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return -1;
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csum = skb_checksum(skb, offs, skb->len - offs, 0);
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*(__sum16 *)(skb->data + csum_offs) = csum_fold(csum);
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skb->ip_summed = CHECKSUM_UNNECESSARY;
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}
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if (skb_is_nonlinear(skb) &&
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skb_shinfo(skb)->nr_frags > IWL_PCIE_MAX_FRAGS(trans_pcie) &&
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__skb_linearize(skb))
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@ -432,24 +322,6 @@ int iwl_trans_pcie_gen2_tx(struct iwl_trans *trans, struct sk_buff *skb,
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spin_lock(&txq->lock);
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if (iwl_queue_space(txq) < txq->high_mark) {
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iwl_stop_queue(trans, txq);
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/* don't put the packet on the ring, if there is no room */
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if (unlikely(iwl_queue_space(txq) < 3)) {
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struct iwl_device_cmd **dev_cmd_ptr;
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dev_cmd_ptr = (void *)((u8 *)skb->cb +
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trans_pcie->dev_cmd_offs);
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*dev_cmd_ptr = dev_cmd;
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__skb_queue_tail(&txq->overflow_q, skb);
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spin_unlock(&txq->lock);
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return 0;
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}
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}
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/* In AGG mode, the index in the ring must correspond to the WiFi
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* sequence number. This is a HW requirements to help the SCD to parse
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* the BA.
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@ -488,18 +360,10 @@ int iwl_trans_pcie_gen2_tx(struct iwl_trans *trans, struct sk_buff *skb,
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*/
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len = sizeof(struct iwl_tx_cmd) + sizeof(struct iwl_cmd_header) +
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hdr_len - IWL_FIRST_TB_SIZE;
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/* do not align A-MSDU to dword as the subframe header aligns it */
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amsdu = ieee80211_is_data_qos(fc) &&
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(*ieee80211_get_qos_ctl(hdr) &
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IEEE80211_QOS_CTL_A_MSDU_PRESENT);
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if (trans_pcie->sw_csum_tx || !amsdu) {
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tb1_len = ALIGN(len, 4);
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/* Tell NIC about any 2-byte padding after MAC header */
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if (tb1_len != len)
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tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
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} else {
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tb1_len = len;
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}
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tb1_len = ALIGN(len, 4);
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/* Tell NIC about any 2-byte padding after MAC header */
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if (tb1_len != len)
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tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
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/*
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* The first TB points to bi-directional DMA data, we'll
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@ -517,15 +381,9 @@ int iwl_trans_pcie_gen2_tx(struct iwl_trans *trans, struct sk_buff *skb,
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goto out_err;
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iwl_pcie_gen2_build_tfd(trans, txq, tb1_phys, tb1_len, false);
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if (amsdu) {
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if (unlikely(iwl_fill_data_tbs_amsdu(trans, skb, txq, hdr_len,
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out_meta, dev_cmd,
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tb1_len)))
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goto out_err;
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} else if (unlikely(iwl_fill_data_tbs(trans, skb, txq, hdr_len,
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out_meta, dev_cmd, tb1_len))) {
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if (unlikely(iwl_fill_data_tbs(trans, skb, txq, hdr_len,
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out_meta, dev_cmd, tb1_len)))
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goto out_err;
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}
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/* building the A-MSDU might have changed this data, so memcpy it now */
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memcpy(&txq->first_tb_bufs[txq->write_ptr], &dev_cmd->hdr,
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@ -536,8 +394,6 @@ int iwl_trans_pcie_gen2_tx(struct iwl_trans *trans, struct sk_buff *skb,
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iwl_pcie_gen2_update_byte_tbl(trans, txq, le16_to_cpu(tx_cmd->len),
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iwl_pcie_gen2_get_num_tbs(trans, tfd));
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wait_write_ptr = ieee80211_has_morefrags(fc);
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/* start timer if queue currently empty */
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if (txq->read_ptr == txq->write_ptr) {
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if (txq->wd_timeout) {
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@ -559,8 +415,9 @@ int iwl_trans_pcie_gen2_tx(struct iwl_trans *trans, struct sk_buff *skb,
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/* Tell device the write index *just past* this latest filled TFD */
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txq->write_ptr = iwl_queue_inc_wrap(txq->write_ptr);
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if (!wait_write_ptr)
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iwl_pcie_gen2_txq_inc_wr_ptr(trans, txq);
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iwl_pcie_gen2_txq_inc_wr_ptr(trans, txq);
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if (iwl_queue_space(txq) < txq->high_mark)
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iwl_stop_queue(trans, txq);
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/*
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* At this point the frame is "transmitted" successfully
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@ -586,7 +443,7 @@ void iwl_pcie_gen2_txq_unmap(struct iwl_trans *trans, int txq_id)
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IWL_DEBUG_TX_REPLY(trans, "Q %d Free %d\n",
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txq_id, txq->read_ptr);
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iwl_pcie_txq_free_tfd(trans, txq);
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iwl_pcie_gen2_free_tfd(trans, txq);
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txq->read_ptr = iwl_queue_inc_wrap(txq->read_ptr);
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if (txq->read_ptr == txq->write_ptr) {
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@ -2080,10 +2080,10 @@ static void iwl_compute_pseudo_hdr_csum(void *iph, struct tcphdr *tcph,
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}
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}
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int iwl_fill_data_tbs_amsdu(struct iwl_trans *trans, struct sk_buff *skb,
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struct iwl_txq *txq, u8 hdr_len,
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struct iwl_cmd_meta *out_meta,
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struct iwl_device_cmd *dev_cmd, u16 tb1_len)
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static int iwl_fill_data_tbs_amsdu(struct iwl_trans *trans, struct sk_buff *skb,
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struct iwl_txq *txq, u8 hdr_len,
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struct iwl_cmd_meta *out_meta,
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struct iwl_device_cmd *dev_cmd, u16 tb1_len)
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{
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struct iwl_tx_cmd *tx_cmd = (void *)dev_cmd->payload;
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struct iwl_trans_pcie *trans_pcie = txq->trans_pcie;
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