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ASoC: cs35l41: Move power initializations to reg_sequence

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ASoC and HDA systems for all revisions of CS35L41 will benefit
from having this initialization, so add it to reg_sequence of
each revision

By moving to reg_sequence all gains are set to zero. And boost,
monitoring parts, and class D amplifier are disabled.

Signed-off-by: Lucas Tanure <tanureal@opensource.cirrus.com>
Link: https://lore.kernel.org/r/20211217115708.882525-4-tanureal@opensource.cirrus.com
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Lucas Tanure 2021-12-17 11:57:01 +00:00 committed by Mark Brown
parent fe120d4cb6
commit 062ce05933
No known key found for this signature in database
GPG Key ID: 24D68B725D5487D0
2 changed files with 8 additions and 15 deletions
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3
sound/soc/codecs/cs35l41-lib.c
View File

@ -17,6 +17,7 @@
static const struct reg_default cs35l41_reg[] = {
{ CS35L41_PWR_CTRL1, 0x00000000 },
{ CS35L41_PWR_CTRL2, 0x00000000 },
{ CS35L41_PWR_CTRL3, 0x01000010 },
{ CS35L41_GPIO_PAD_CONTROL, 0x00000000 },
{ CS35L41_SP_ENABLES, 0x00000000 },
@ -46,7 +47,7 @@ static const struct reg_default cs35l41_reg[] = {
{ CS35L41_CLASSH_CFG, 0x000B0405 },
{ CS35L41_WKFET_CFG, 0x00000111 },
{ CS35L41_NG_CFG, 0x00000033 },
{ CS35L41_AMP_GAIN_CTRL, 0x00000273 },
{ CS35L41_AMP_GAIN_CTRL, 0x00000000 },
{ CS35L41_GPIO1_CTRL1, 0xE1000001 },
{ CS35L41_GPIO2_CTRL1, 0xE1000001 },
{ CS35L41_MIXER_NGATE_CFG, 0x00000000 },

20
sound/soc/codecs/cs35l41.c
View File

@ -1288,6 +1288,8 @@ static const struct reg_sequence cs35l41_reva0_errata_patch[] = {
{ CS35L41_DSP1_XM_ACCEL_PL0_PRI, 0x00000000 },
{ 0x00000040, 0x0000CCCC },
{ 0x00000040, 0x00003333 },
{ CS35L41_PWR_CTRL2, 0x00000000 },
{ CS35L41_AMP_GAIN_CTRL, 0x00000000 },
};
static const struct reg_sequence cs35l41_revb0_errata_patch[] = {
@ -1301,6 +1303,8 @@ static const struct reg_sequence cs35l41_revb0_errata_patch[] = {
{ CS35L41_DSP1_XM_ACCEL_PL0_PRI, 0x00000000 },
{ 0x00000040, 0x0000CCCC },
{ 0x00000040, 0x00003333 },
{ CS35L41_PWR_CTRL2, 0x00000000 },
{ CS35L41_AMP_GAIN_CTRL, 0x00000000 },
};
static const struct reg_sequence cs35l41_revb2_errata_patch[] = {
@ -1314,6 +1318,8 @@ static const struct reg_sequence cs35l41_revb2_errata_patch[] = {
{ CS35L41_DSP1_XM_ACCEL_PL0_PRI, 0x00000000 },
{ 0x00000040, 0x0000CCCC },
{ 0x00000040, 0x00003333 },
{ CS35L41_PWR_CTRL2, 0x00000000 },
{ CS35L41_AMP_GAIN_CTRL, 0x00000000 },
};
static const struct reg_sequence cs35l41_fs_errata_patch[] = {
@ -1556,20 +1562,6 @@ int cs35l41_probe(struct cs35l41_private *cs35l41,
goto err;
}
ret = regmap_update_bits(cs35l41->regmap, CS35L41_PWR_CTRL2,
CS35L41_AMP_EN_MASK, 0);
if (ret < 0) {
dev_err(cs35l41->dev, "Write CS35L41_PWR_CTRL2 failed: %d\n", ret);
goto err;
}
ret = regmap_update_bits(cs35l41->regmap, CS35L41_AMP_GAIN_CTRL,
CS35L41_AMP_GAIN_PCM_MASK, 0);
if (ret < 0) {
dev_err(cs35l41->dev, "Write CS35L41_AMP_GAIN_CTRL failed: %d\n", ret);
goto err;
}
ret = cs35l41_set_pdata(cs35l41);
if (ret < 0) {
dev_err(cs35l41->dev, "Set pdata failed: %d\n", ret);