forked from Minki/linux
drm/i915: Refactor LPT-H VGA dotclock disabling
Extract the LPT-H VGA dotclock disable to a separate function in anticipation of further use. While at it move the sb_lock locking inwards when enabling the VGA dotclock, as it's only needed to protect the sideband accesses. v2: Keep the PIXCLK_GATE_GATE name for 0 (Paulo) Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1449260494-14449-1-git-send-email-ville.syrjala@linux.intel.com
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@ -3940,6 +3940,21 @@ static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
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return 0;
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}
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static void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
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{
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u32 temp;
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I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
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mutex_lock(&dev_priv->sb_lock);
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temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
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temp |= SBI_SSCCTL_DISABLE;
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intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
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mutex_unlock(&dev_priv->sb_lock);
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}
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/* Program iCLKIP clock to the desired frequency */
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static void lpt_program_iclkip(struct drm_crtc *crtc)
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{
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@ -3949,18 +3964,7 @@ static void lpt_program_iclkip(struct drm_crtc *crtc)
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u32 divsel, phaseinc, auxdiv, phasedir = 0;
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u32 temp;
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mutex_lock(&dev_priv->sb_lock);
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/* It is necessary to ungate the pixclk gate prior to programming
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* the divisors, and gate it back when it is done.
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*/
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I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
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/* Disable SSCCTL */
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intel_sbi_write(dev_priv, SBI_SSCCTL6,
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intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
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SBI_SSCCTL_DISABLE,
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SBI_ICLK);
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lpt_disable_iclkip(dev_priv);
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/* 20MHz is a corner case which is out of range for the 7-bit divisor */
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if (clock == 20000) {
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@ -4000,6 +4004,8 @@ static void lpt_program_iclkip(struct drm_crtc *crtc)
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phasedir,
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phaseinc);
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mutex_lock(&dev_priv->sb_lock);
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/* Program SSCDIVINTPHASE6 */
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temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
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temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
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@ -4021,12 +4027,12 @@ static void lpt_program_iclkip(struct drm_crtc *crtc)
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temp &= ~SBI_SSCCTL_DISABLE;
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intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
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mutex_unlock(&dev_priv->sb_lock);
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/* Wait for initialization time */
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udelay(24);
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I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
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mutex_unlock(&dev_priv->sb_lock);
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}
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static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
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